Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge UnitThe PCI master target interface is responsible for issuing the write completion transaction to a PCIagent using the data in the DWC Queue and the address/command from the Transaction Queue.The data flow for a delayed write transaction on the target bus is summarized in the followingstatements:• The master interface on the target PCI bus will request the PCI bus when after address and datafrom the request cycle have been received and ordering has been satisfied (see Section 4.7.2).Once the bus is granted, the target PCI interface will write the PCI address to the PCI bus andwait for the transaction to be claimed.• When an address parity error is detected by an agent on the bus, SERR# may be asserted.• When the transaction on the bus receives a master-abort, the appropriate master abortcondition is loaded into the DWC queue for return to the PCI master on the initiating bus.Refer to Section 4.10.1.4 for master-abort conditions.• When the PCI target signals a Retry or Disconnect, the master interface will return to idle.When the PCI target signals claims the transaction, the 32-bit data is transferred to the target ina single data phase (all delayed writes are performed as 32-bit operations.). The master/targetresponse is captured for return to the master on the initiating bus. The following conditions arepossible:— Master Completion - Normal Completion— Target Abort— Data Parity ErrorThe Write_Complete flag is set indicating to the initiating interface that the writecompletion cycle is complete.4-58 Developer’s Manual