Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge UnitTable 4-46. Extended Bridge Control Register - EBCR (Sheet 2 of 2)IOPAttributes15 12 8 4 0rv rv rv rw ro ro ro ro rv rw rw rv rw rw rw rwPCIAttributesrvrvrvrwrororororvrw rwrvrwrorw rwPCI Configuration Offset40 - 41HIntel ® 80200 Processor Local Bus Address0000 1040HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description05 0 2 complete, and the ATU slave interfaces will proceed to an idle state. All future slave transactionswill master abort, with the exception of the completion cycle for the transaction that set the ResetReset Internal Bus - This bit controls the reset of the Intel ® 80200 processor and all units on the internalbus. When set:• The PCI-to-PCI Bridge Unit is not reset. Upstream and downstream bridge I/O and memorytransactions are unaffected during the IB reset.• All current PCI transactions being mastered by the ATU and DMA will complete, and the ATU andDMA master interfaces will proceed to an idle state. No additional transactions will be mastered bythese units until the IB reset is complete.• All current transactions being slaved by the ATU on either the PCI bus or the internal bus willInternal Bus bit in the EBCR.• When the value of the Intel ® 80312 I/O companion chip Reset bit in the EBCR (upon normal reset)is set, the Intel ® 80200 processor will be held in reset when the IB reset is complete.• The Bridge and the ATU will ignore configuration cycles, and they will appear as master aborts for:32 Internal Bus clocks + the number of Internal Bus clocks needed to finish all ATU and DMAtransactions that will complete before the IB reset (as described in the above text).• The Intel ® 80312 I/O companion chip hardware will clear this bit after the reset operationcompletes.04 0 2 Reserved.03 1 2Memory Read commands are to prefetchable memory. When this bit is clear, the Bridge assumes thatupstream Memory Read commands are to non-prefetchable memory. (Modifying this bit, while theUpstream Prefetchable Memory Enable - When this bit is set, the Bridge assumes that upstreambridge is enabled may cause unknown behavior.)0201Varies withexternal stateof RETRY pinat PrimaryPCI bus resetVaries withexternal stateofRST_MODE#pin at PrimaryPCI bus resetConfiguration Cycle Retry - When this bit is set, the Primary PCI interface of the Intel ® 80312 I/Ocompanion chip will respond to all configuration cycles with a Retry condition. When clear, the Intel ®80312 I/O companion chip will respond to the appropriate configuration cycles.The default condition for this bit is based on the external state of the RETRY pin at the rising edge ofP_RST#. When the external state of the pin is high, the bit is set. When the external state of the pin islow, the bit is cleared.Intel ® 80312 I/O companion chipReset - This bit is set to its default value by the hardware when eitherP_RST# is asserted or the Reset Local Bus bit in the EBCR is set. When this bit is set, the Intel ® 80200processor is being held in reset. Software cannot set this bit. Software will be required to clear this bit todeassert Intel ® 80200 processor reset.The default condition for this bit is based on the external state of the RST_MODE# pin at the rising edgeof P_RST#. When the external state of the pin is low, the default value of this bit is set. When theexternal state of the pin is high, the default value of this bit is clear.00 0 2bridge interface. All memory write transactions are processed as Delayed Write transactions. When thisbit is clear, the bridge is allowed to post write transactions. (Modifying this bit, while the bridge isPostingDisable-Whenthisbitisset,thebridgeisnotallowedtopostwritetransactionsfromeitherenabled may cause unknown behavior.)4-110 Developer’s Manual