Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.7.4 Primary ATU Status Register - PATUSRThe Primary ATU Status Register bits adhere to the PCI Local Bus Specification, Revision 2.2definitions. The read/clear bits can only be set by internal hardware and cleared by either a resetcondition or by writing a 1 2 to the register.Table 5-31. Primary ATU Status Register - PATUSR (Sheet 1 of 2)IOPAttributes15 12 8 4 0rc rc rc rc rc ro ro rc ro ro ro ro rv rv rv rvPCIAttributesrcrcrcrcrcrororcrororororvrvrvrvIntel ® 80200 Processor Local Bus Address1206HPCI Configuration Address Offset06H - 07HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description15 0 2 • Read Data Parity Error when the PATU, DMA Channel 0, or DMA Channel1 is a master (outboundDetected Parity Error - set when a parity error is detected on the primary PCI bus even when thePATUCMD register’s Parity Error Response bit is cleared. Set under the following conditions:• Write Data Parity Error when the PATU is a slave (inbound write).read).• Any Address Parity Error on the Primary Bus (including one generated by the PATU or DMAChannels 0 &1).14 0 2 P_SERR# Asserted - set when P_SERR# is asserted on the PCI bus by the primary ATU.13 0 2Master Abort - set when a transaction initiated by the primary ATU PCI master interface, DMA Channel0, or DMA Channel 1 ends in a Master-Abort. Setting of this bit due to an error condition from eitherDMA Channel does not cause an ATU interrupt to the Intel ® 80200 processor.12 0 2Target Abort (master) - set when a transaction initiated by the primary ATU PCI master interface, DMAChannel 0 master interface or DMA Channel 1 master interface ends in a target abort. Setting of this bitdue to an error condition from either DMA Channel does not cause an ATU interrupt to the Intel ® 80200processor.Target Abort (target) - set when the primary ATU interface, acting as a target, terminates the transaction11 0 2 on the primary PCI bus with a target abort.10:09 10 2DEVSEL# Timing - These bits are read-only and define the slowest DEVSEL# timing for a target device(except configuration accesses).00 2 =Fast01 2 =Medium10 2 =Slow11 2 = ReservedIn general, the primary and secondary ATU interfaces use Medium timing.However, when the Messaging Unit is enabled and the Inbound/Outbound Message Ports (Primary ATUInbound Window offset 40h) are hit with a 64-bit access (P_REQ64# asserted), the need to pre-decodethe P_C/BE[3:0]# bus forces the PATU to claim the access using Slow decode timing.Though this occurrence is rather unlikely, the PCI Local Bus Specification, Revision 2.2 requires that thisfield of the status register indicate the slowest DEVSEL# possible by a target device.In the event that a subtractive decode agent is present on the PATU bus segment, the indication that thePATU could claim positively with Slow decode prevents the users of this bus from programming thesubtractive decode agent to claim with Slow decode timing.5-64 Developer’s Manual