Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.5.5 64-Bit Address Decoding - Dual Address CyclesThe bridge unit supports the dual address cycle (DAC) command for 64-bit addressing on theSecondary interface of the bridge unit only. Dual address cycle commands allow 64-bit addressingby using two PCI address phases; the first one for the lower 32 bits and the second one for thehigher 32 bits. The DAC command is also used by the bridge Primary PCI interface to forwardDAC cycles that appear on the secondary bus upstream.The bridge unit decodes and forwards all dual address cycle commands from the Secondary to thePrimary interface regardless of the address ranges defined in the MBR/MLR and PMBR/PMLRregister pairs. DAC cycles are restricted to PCI memory commands only. I/O and configurationcycles are not supported in the greater than 4 GB address space. All DAC transactions are treatedas prefetchable and adhere to the prefetch data amounts defined in Table 4-13.The bridge unit defaults to Subtractive Decode timing for claiming dual address cycle commands.Subtractive Decode timing is defined as the assertion of DEVSEL# on the fourth clock after theaddress phase, the fifth clock after FRAME#, for DAC cycles. When the Secondary DAC MediumDecode Enable bit is set in the EBCR, the Secondary interface of the bridge claims all DACtransactions with medium decode timing.The Primary interface will not forward dual address cycle commands to the Secondary interface.The operation of DAC mode addressing for 32-bit or 64-bit buses, as defined by the PCI Local BusSpecification, Revision2.2,isshowninFigure 4-8. For 32-bit bus operation or for a DAC requestinitiated from a 32-bit device on a 64-bit bus, AD[63:32] and C/BE[7:4]# are ignored. As a masteron the Primary PCI bus, the bridge unit extends the address phase to two clock cycles. In the firstcycle, the bridge drives the low order 32-bits of address on AD[31:0] and the DAC PCI command(1101 2 )onC/BE[3:0]#. In the second address cycle, the bridge drives the high order 32-bit ofaddress on AD[31:0] and the actual PCI read/write command on C/BE[3:0]#.For 64-bit bus operation as a target on the Secondary bus, the bridge unit does not decode the highorder address bits driven on S_AD[63:32] during the first address phase of the DAC cycle. TheSecondary bridge interface waits for the second address phase to capture the complete 64-bitaddress and the actual PCI command for the transaction. As a master on the Primary PCI businterface, the bridge operates as defined in Figure 4-8 and drives the high order 32 bits onP_AD[63:32] and the actual PCI command on P_C/BE[7:4]# during the first address phase of theDAC cycle. Both address phases as defined for a 32-bit bus are still performed.The response to DAC commands on the Secondary interface may be modified by the followingregister bit from the bridge configuration space:• the Master Enable bit in the Primary Command Register (PCR)• the Posting Disable bit in the Extended Bridge Control Register (EBCR)The Master Enable bit in the PCR must be set to allow the Primary interface to master PCItransactions.When the Posting Disable bit is set, the Secondary interface of the bridge unit will not accept anyDAC write transactions at all.4-22 Developer’s Manual