Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipI 2 C Bus Interface Unit12.8.4 I 2 C Data Buffer Register- IDBRThe I 2 C Data Buffer Register is used by the Intel ® 80200 processor to transmit and receive datafrom the I 2 C bus. The accesses the IDBR by the Intel ® 80200 processor on one side and by the I 2 Cshift register on the other. Data coming into the I 2 C Bus Interface Unit is received into the IDBRafter a full byte has been received and acknowledged. Data going out of the I 2 C Bus Interface Unitis written to the IDBR by the Intel ® 80200 processor and sent to the serial bus.When the I 2 C Bus Interface Unit is in transmit mode (master or slave), the Intel ® 80200 processorwrites data to the IDBR over the internal bus. This occurs when a master transaction is initiated orwhen the IDBR Transmit Empty Interrupt is signalled. Data is moved from the IDBR to the shiftregister when the Transfer Byte bit is set. The IDBR Transmit Empty Interrupt is signalled (whenenabled) when a byte has been transferred on the I 2 C bus and the acknowledge cycle is complete.When the IDBR is not written by the Intel ® 80200 processor (and a STOP condition was not inplace) before the I 2 C bus is ready to transfer the next byte packet, the I 2 C Bus Interface Unit insertswait states until the Intel ® 80200 processor writes the IDBR and sets the Transfer Byte bit.When the I 2 C Bus Interface Unit is in receive mode (master or slave), the processor reads IDBRdata over the internal bus. This occurs when the IDBR Receive Full Interrupt is signalled. The datais moved from the shift register to the IDBR when the Ack cycle is complete. The I 2 CBusInterface Unit inserts wait states until the IDBR has been read. Refer to Section 12.3.3, “I 2 CAcknowledge” on page 12-11 for acknowledge pulse information in receiver mode. After theIntel ® 80200 processor reads the IDBR, the Ack/Nack Control bit is written and the Transfer Bytebit is written, allowing the next byte transfer to proceed on the I 2 C Bus. The IDBR register is 00Hafter reset.Table 12-12.I 2 C Data Buffer Register - IDBRIOPAttributes31rvrvrv28 24 20 16 12 8 4 0rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rw rw rw rw rw rw rw rwPCIAttributesnanananananananananananananananananananananananananananananananaIntel ® 80200 Local Bus Address168CHAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description31:08 000000H Reserved07:00 00H I 2 C Data Buffer: Buffer for I 2 C bus send/receive data.Developer’s Manual 12-33