Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.2 ATU Address TranslationThe primary ATU and the secondary ATU support transactions from both directions through theIntel ® 80312 I/O companion chip. The primary ATU allows PCI masters on the primary PCI bus toinitiate transactions to the Intel ® 80312 I/O companion chip internal bus and allows the Intel ®80200 processor based on Intel ® XScale microarchitecture (ARM* architecture compliant) toinitiate transactions to the primary PCI bus. The secondary ATU performs the same function, buton the secondary PCI bus and for secondary PCI bus masters.The ATUs implement an address windowing scheme to determine which addresses to claim andtranslate to the appropriate bus.• The address windowing mechanism for inbound translation is described in Section 5.2.1.1,“Inbound Address Translation” on page 5-6• The address windowing mechanism for outbound translation is described in Section 5.2.2.1,“Outbound Address Translation” on page 5-15The ATU has the ability to handle multiple inbound PCI transactions simultaneously. The ATUmay contain up to four PCI memory writes up to the data queue size of the ATU (PATU or SATU).Each ATU is also capable of handling two outstanding delayed read transactions. Refer toFigure 5-2 and Section 5.5 for details of the ATU queue architecture.The primary ATU contains a data path between the primary PCI bus and the internal bus.Connecting the primary ATU in this manner enables data transfers to occur without requiring anyresources on the secondary PCI bus. The secondary ATU contains a data path between thesecondary PCI bus and the internal bus. The secondary ATU allows secondary PCI bus masters toaccess the internal bus and Intel ® 80312 I/O companion chip local memory. These transactions areinitiated by a secondary bus master and do not require any bandwidth on the primary PCI bus.The ATU units allow for recognition and generation of multiple PCI cycle types. Table 5-1 showsthe PCI commands supported for both inbound and outbound ATU transactions. The type ofoperation seen by the ATU on inbound transactions is determined by the PCI master (on eitherprimary or secondary bus) who initiates the transaction. Claiming an inbound transaction dependson the address range programmed within the inbound translation window. The type of transactionused by the ATU on outbound transactions is determined by the Intel ® 80200 processor localaddress and the fixed outbound windowing scheme. See Section 5.2.2.1, “Outbound AddressTranslation” on page 5-15 for the full details on outbound PCI cycle selection.Both ATUs support the 64-bit addressing specified by the PCI Local Bus Specification,Revision 2.2. This 64-bit addressing extension is for outbound data transactions only (i.e., datatransfers initiated by the Intel ® 80200 processor). This is in addition to the 64-bit data extensionssupported by the Intel ® 80312 I/O companion chip. Refer to Section 5.2.5 for details of 64-bit PCIoperation. Neither ATU supports exclusive access using the PCI LOCK# signal.5-4 Developer’s Manual