Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPerformance Monitoring Unit11.2.2.2 Duration EventsFor a duration event, the counter counts the number of clocks during which a particular conditionor set of conditions is true. Acquisition latency measurements comprise:• Arbitration Latency: This represents the elapsed time between the bus master’s request touse the bus until the requesting master is granted the bus.• Bus Acquisition Latency: This represents the elapsed time between the requesting bus masterbeing granted the bus and the current bus master surrendering the bus allowing the requestingbus master to initiate the next transaction.Table 11-2 lists the various duration events that are monitored on the Intel ® 80312 I/O companionchip.Table 11-2.Duration EventsObserved InterfaceMonitored EventNumber clocks the PCI bus is busyNumber of clocks the PCI bus is idleAcquisition latency and ownership metrics for the PATU and SATUPrimary and SecondaryPCI busesAcquisition latency and ownership metrics for DMA Ch-0, Ch-1 and Ch-2Acquisition latency and ownership metrics for the BridgeAcquisition latency and ownership metrics for external masters 0..5 and the Intel ®80312 I/O companion chip (summation of all internal masters on secondaryinterface) on the secondary PCI busAcquisition latency and ownership metrics for the Intel ® 80312 I/O companionchip on the primary PCI busAcquisition latency and ownership metrics for the Intel ® 80200 processorIntel ® 80312 I/Ocompanion chip internalbusAcquisition latency and ownership metrics for DMA Channels 0,1 and 2Acquisition latency and ownership metrics for Application AcceleratorAcquisition latency and ownership metrics for the PATUAcquisition latency and ownership metrics for the SATU11-4 Developer’s Manual