Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.15.26 Secondary Bridge Interrupt Status Register - SBISRThe Secondary Bridge Interrupt Status Register notifies the Intel ® 80200 processor of the source ofa Secondary Bridge interface interrupt. In addition, this register is written to clear the source of theinterrupt to the interrupt unit of the Intel ® 80312 I/O companion chip (see Section 2.3, “Intel ®80312 I/O Companion Chip Interrupts” on page 2-2). All bits in this register are Read/Clear fromthe PCI bus and the local bus.Bits 5:0 are a direct reflection of bits 15:11 and bit 8 (respectively) of the Secondary StatusRegister (these bits are set at the same time by hardware but need to be cleared independently).Bit 6 is set when software sets and subsequently clears the Secondary Bus Reset bit in the BCR.The conditions that result in a Secondary Bridge interrupt are cleared by writing a “1” to theappropriate bits in this register.The individual setting of the bits within the SBISR can be masked through the bits 3, 15:11, and 5of the SDER. Refer to Section 4.15.34 for details.Table 4-49.Secondary Bridge Interrupt Status Register - SBISRIOPAttributes31rvrvrv28 24 20 16 12 8 4 0rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rc rc rc rc rc rc rcPCIAttributesrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrcrcrcrcrcrcrcPCI Configuration Offset48 - 4BHIntel ® 80200 Processor Local Bus Address0000 1048HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description31:07 0000000H Reserved.06 0 2Secondary Bus Reset Occurred - This bit is set when the bridge senses the deassertion (by softwareonly) of bit 6, Secondary Bus Reset, in the BCR.Detected Parity Error - This bit is set when a parity error is detected during a data transfer on theSecondary bus even when parity handling is disabled. Set under the following conditions:• Write Data Parity Error when the Secondary interface of the Bridge is a slave (upstream write).05 0 2• Read Data Parity Error when the Secondary interface of the Bridge is a master (downstream read).• Any Address Parity Error on the Secondary Bus (including one generated by the Secondaryinterface of the Bridge).04 0 2 Received System Error - This bit is set when S_SERR# is detected on the Secondary PCI bus.PCI Master Abort - This bit is set whenever a transaction initiated by the Secondary master interface03 0 2 ends in a Master-Abort.PCI Target Abort (Master) - This bit is set whenever a transaction initiated by the Secondary master02 0 2 interface ends in a Target-Abort.PCI Target Abort (Target) - This bit is set whenever the Secondary interface, acting as a target,01 0 2 terminates the transaction on the PCI bus with a Target-Abort.00 0 21. the bus agent asserted S_PERR# itself or observed S_PERR# asserted2. the agent setting the bit acted as the bus master for the operation in which the error occurredPCI Master Parity Error - The Secondary interface sets this bit when three conditions are met:3. the Secondary Parity Error Response bit (BCR Register) is set4-114 Developer’s Manual