Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipApplication Accelerator Unit10.3.2 Chain Descriptor Format (Four Source Addresses)All transfers are controlled by chain descriptors located in local memory. A chain descriptorcontains the necessary information to complete one transfer. A single transfer has only one chaindescriptor in memory. Chain descriptors can be linked together to form more complex operations.To perform a transfer, one or more chain descriptors must first be written to Intel ® 80200 processorlocal memory. Figure 10-3 shows the format of an individual chain descriptor. Every descriptorrequires eight contiguous words in Intel ® 80200 processor local memory and is required to bealigned on an 8-word boundary. All eight words are required.Figure 10-3.Chain Descriptor FormatChain Descriptor in Intel ® 80200 processorNext Descriptor Address (NDA)Source Address (SAR1)Source Address (SAR2)Source Address (SAR3)Source Address (SAR4)Destination Address (DAR)Byte Count (BC)Descriptor Control (DC)DescriptionAddress of Next Chain DescriptorSource Address for first block of dataSource Address for second block of dataSource Address for third block of dataSource Address for fourth block of dataDestination AddressNumber of bytesDescriptor ControlEach word in the chain descriptor is analogous to control register values. Bit definitions for thewords in the chain descriptor are the same as for the control registers.• The first word is the Intel ® 80200 processor local memory address of the next chain descriptor.A value of zero specifies the end of the chain. This value is loaded into the Accelerator NextDescriptor Address Register. Because chain descriptors must be aligned on an 8-wordboundary, the unit may ignore bits 04:00 of this address.• The second word is the address of the first block of data resident in Intel ® 80200 processorlocal memory. This address is driven on the internal bus. This value is loaded into the SourceAddress Register 1.• The third word is the address of the second block of data resident in Intel ® 80200 processorlocal memory. This address is driven on the internal bus. This value is loaded into the SourceAddress Register 2.• The fourth word is the address of the third block of data resident in Intel ® 80200 processorlocal memory. This address is driven on the internal bus. This value is loaded into the SourceAddress Register 3.• The fifth word is the address of the fourth block of data resident in Intel ® 80200 processorlocal memory. This address is driven on the internal bus. This value is loaded into the SourceAddress Register 4.10-4 Developer’s Manual