Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI and Peripheral Interrupt Controller Unit2.7 Register DefinitionsAll registers are visible as the Intel ® 80312 I/O companion chip memory mapped registers and canbe accessed through the internal memory bus. Each is a 32-bit register and is memory-mapped inthe internal bus memory space. The memory-mapped addresses of the interrupt control registersare found in Appendix A, “Peripheral Memory-Mapped Registers”.There are four control and status registers for the PCI And Peripheral Interrupt Controller:• PCI Interrupt Routing Select Register• FIQ1 Interrupt Status Register• FIQ2 Interrupt Status Register• IRQ Interrupt Status RegisterThe PCI Interrupt Routing Select Register is accessible from the internal memory bus and alsoduring PCI configuration cycles through the PCI configuration register space (function #0). SeeChapter 5, PCI Address Translation Unit for additional information regarding the PCIconfiguration cycles that access the PCI Interrupt Routing Select Register. The programmerinterface to the interrupt controller is through memory-mapped control registers. Table 2-7describes these registers.Table 2-7.Interrupt Control Registers AddressesRegister Name Description AddressPIRSR PCI Interrupt Routing Select Register 0000 1050HFIQ1ISR FIQ1 Interrupt Status Register 0000 1708HFIQ2ISR FIQ2 Interrupt Status Register 0000 1704HIRQISR IRQ Interrupt Status Register 0000 1700H2-10 Developer’s Manual