Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion Chip6-15 MU Configuration Register - MUCR ........................................................................................6-266-16 Queue Base Address Register - QBAR...................................................................................6-276-17 Inbound Free Head Pointer Register - IFHPR .........................................................................6-286-18 Inbound Free Tail Pointer Register - IFTPR ............................................................................6-296-19 Inbound Post Head Pointer Register - IPHPR .........................................................................6-306-20 Inbound Post Tail Pointer Register - IPTPR ............................................................................6-316-21 Outbound Free Head Pointer Register - OFHPR ....................................................................6-326-22 Outbound Free Tail Pointer Register - OFTPR........................................................................6-336-23 Outbound Post Head Pointer Register - OPHPR ....................................................................6-346-24 Outbound Post Tail Pointer Register - OPTPR........................................................................6-356-25 Index Address Register - IAR ..................................................................................................6-367-1 Bus Master / Programmed Priorities..........................................................................................7-47-2 Bus Arbitration Example – Three Bus Masters..........................................................................7-47-3 Bus Arbitration Example – Six Bus Masters ..............................................................................7-57-4 Arbitration Flow..........................................................................................................................7-77-5 Arbitration Block and Reset Signals ........................................................................................7-117-6 Secondary Arbiter Register Table............................................................................................7-127-7 Secondary Arbitration Control Register - SACR ......................................................................7-137-8 2-Bit Priorities ..........................................................................................................................7-137-9 Internal Arbitration Control Register - IACR.............................................................................7-147-10 Master Latency Timer Register - MLTR...................................................................................7-157-11 Multi-Transaction Timer Register - MTTR ...............................................................................7-168-1 Byte Enable Encodings For Read Transactions ........................................................................8-48-2 Word Enable Encodings For Write Transactions.......................................................................8-48-3 Intel ® 80312 I/O Companion Chip Internal Bus Command Summary .......................................8-59-1 DMA Registers...........................................................................................................................9-49-2 DMA Interrupt Summary ..........................................................................................................9-229-3 DMA Controller Unit Registers.................................................................................................9-259-4 Channel Control Register - CCR .............................................................................................9-269-5 Channel Status Register - CSR ...............................................................................................9-279-6 Next Descriptor Address Register - NDAR ..............................................................................9-299-7 Descriptor Address Register - DAR .........................................................................................9-309-8 Byte Count Register - BCR......................................................................................................9-319-9 PCI Address Register - PADR .................................................................................................9-329-10 PCI Upper Address Register - PUADR....................................................................................9-339-11 Intel ® 80200 Processor Local Address Register - LADR.........................................................9-349-12 Descriptor Control Register - DCR ..........................................................................................9-359-13 PCI Commands .......................................................................................................................9-3610-1 Register Description ................................................................................................................10-310-2 AAU Interrupts .......................................................................................................................10-2110-3 Application Accelerator Unit Registers ..................................................................................10-2310-4 Accelerator Control Register - ACR.......................................................................................10-2410-5 Accelerator Status Register - ASR ........................................................................................10-2510-6 Accelerator Descriptor Address Register - ADAR .................................................................10-2610-7 Accelerator Next Descriptor Address Register - ANDAR ......................................................10-2710-8 Intel ® 80200 Processor Source Address Register - SARx ....................................................10-2810-9 Intel ® 80200 Processor Destination Address Register - DAR ...............................................10-2910-10 Accelerator Byte Count Register - ABCR ..............................................................................10-3010-11 Accelerator Descriptor Control Register - ADCR...................................................................10-3111-1 Occurrence Events ..................................................................................................................11-3Developer’s Manualxxv