Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPerformance Monitoring Unit11.3.6.3 M5_AA_acqThis duration event counts the number of clocks spent by the Application Accelerator (AA)acquiring the internal bus interface. The counter increments on every clock cycle after the AA hasrequested use of the bus but has not actively driven the bus as a master. The counter alsoincrements for all clock cycles when this agent’s Request Signal is asserted but bus ownershipcurrently belongs to another master. This is an event primitive, used in conjunction with anotherevent primitive (number of grants granted to AA) to calculate the average acquisition latency.11.3.6.4 M5_AA_ownThis duration event counts the duration for which the AA is the master on the internal bus. Thecounter increments on every clock cycle during which the AA is the bus master.11.3.6.5 M5_DMA0_acqThis duration event counts the number of clocks spent by DMA Ch-0 acquiring the internal businterface. The counter increments on every clock cycle after Ch-0 has requested use of the bus buthas not actively driven the internal bus as a master. The counter also increments for all clock cycleswhen this agent’s Request Signal is asserted but bus ownership currently belongs to another master.This is an event primitive, used in conjunction with another event primitive (number of grantsgranted to Ch-0) to calculate the average acquisition latency.11.3.6.6 M5_DMA0_ownThis duration event counts the duration for which DMA Ch-0 is the master on the internal bus. Thecounter increments on every clock cycle during which Ch-0 is the bus master.11.3.6.7 M5_DMA1_acqThis duration event counts the number of clocks spent by DMA Ch-1 acquiring the internal businterface. The counter increments on every clock cycle after Ch-1 has requested use of the bus buthas not actively driven the internal bus as a master. The counter also increments for all clock cycleswhen this agent’s Request Signal is asserted but bus ownership currently belongs to another master.This is an event primitive, used in conjunction with another event primitive (number of grantsgranted to Ch-1) to calculate the average acquisition latency.11.3.6.8 M5_DMA1_ownThis duration event counts the duration for which DMA Ch-1 is the master on the internal bus. Thecounter increments on every clock cycle during which Ch-1 is the bus master.11.3.6.9 M5_DMA2_acqThis duration event counts the number of clocks spent by DMA Ch-2 acquiring the internal businterface. The counter increments on every clock cycle after Ch-2 has requested use of the bus buthas not actively driven the internal bus as a master. The counter also increments for all clock cycleswhen this agent’s Request Signal is asserted but bus ownership currently belongs to another master.This is an event primitive, used in conjunction with another event primitive (number of grantsgranted to Ch-2) to calculate the average acquisition latency.11-16 Developer’s Manual