Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipMessaging Unit6.3 Message RegistersMessages can be sent and received by the Intel ® 80200 processor through the use of the MessageRegisters. When written, the Message Registers may cause an interrupt to be generated to either theIntel ® 80200 processor or the PCI interrupt signals. Inbound messages are sent by the host processorand received by the Intel ® 80200 processor. Outbound messages are sent by the Intel ® 80200processor and received by the host processor.The interrupt status for outbound messages is recorded in the Outbound Interrupt Status Register.Interrupt status for inbound messages is recorded in the Inbound Interrupt Status Register.6.3.1 Outbound MessagesWhen an outbound message register is written by the Intel ® 80200 processor, an interrupt may begenerated on the P_INTA#, P_INTB#, P_INTC#, or P_INTD# interrupt pins. Which interrupt pinused is determined by the value of the ATU Interrupt Pin Register (Chapter5,“PCIAddressTranslation Unit”).The PCI interrupt is recorded in the Outbound Interrupt Status Register. The interrupt causes theOutbound Message Interrupt bit to be set in the Outbound Interrupt Status Register. This is aRead/Clear bit that is set by the MU hardware and cleared by software.The interrupt is cleared when an external PCI agent writes a value of “1” to the Outbound MessageInterrupt bit in the Outbound Interrupt Status Register to clear the bit.The interrupt may be masked by the Mask bits in the Outbound Interrupt Mask Register.6.3.2 Inbound MessagesWhen an inbound message register is written by an external PCI agent, an interrupt may begenerated to the Intel ® 80200 processor. The interrupt may be masked by the Mask bits in theInbound Interrupt Mask Register.The Intel ® 80200 processor interrupt is recorded in the Inbound Interrupt Status Register. Theinterrupt causes the Inbound Message Interrupt bit to be set in the Inbound Interrupt StatusRegister. This is a Read/Clear bit that is set by the MU hardware and cleared by software.The interrupt is cleared when the Intel ® 80200 processor writes a value of “1” to the InboundMessage Interrupt bit in the Inbound Interrupt Status Register.Developer’s Manual 6-5