Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipApplication Accelerator Unit10.3.6 Scatter Gather TransfersThe Application Accelerator can be used to perform typical scatter gather transfers. This consistsof programming the chain descriptors to gather data which may be located in non-contiguousblocks of memory. The chain descriptor specifies the destination location such that once all datahas been processed, the data is contiguous in memory. Figure 10-9 shows how the destinationpointers can gather data.10.3.7 Synchronizing a Program to Chained OperationAny operation involving the AAU can be synchronized to a program executing on the Intel ® 80200processor through the use of processor interrupts. The AAU generates an interrupt to the Intel ®80200 processor under certain conditions. They are:1. [Interrupt & Continue] The AAU completes processing a chain descriptor and the AcceleratorNext Descriptor Address Register (ANDAR) is non-zero. When the Interrupt Enable bitwithin the Accelerator Descriptor Control Register (ADCR) is set, an interrupt is generated tothe Intel ® 80200 processor. This interrupt is for synchronization purposes. The AAU sets theEnd Of Transfer Interrupt flag in the Accelerator Status Register (ASR). Since it is not the lastchain descriptor in the list, the AAU starts to process the next chain descriptor withoutrequiring any processor interaction.2. [End of Chain] The AAU completes processing a chain descriptor and the Accelerator NextDescriptor Address Register is zero specifying the end of the chain. When the InterruptEnable bit within the ADCR is set, an interrupt is generated to the Intel ® 80200 processor. TheAAU sets the End Of Chain Interrupt flag in the ASR.3. [Error] An error condition occurs (refer to Section 10.9, “Error Conditions” on page 10-22 forApplication Accelerator error conditions) during a transfer. The AAU halts operation on thecurrent chain descriptor and not proceed to the next chain descriptor.Each chain descriptor can independently set the Interrupt Enable bit in the Descriptor Controlword. This bit enables an independent interrupt once a chain descriptor is processed. This bit canbe set or clear within each chain descriptor. Control of interrupt generation within each descriptoraids in synchronization of the executing software with XOR operation.Figure 10-10 shows two examples of program synchronization. The left column shows programsynchronization based on individual chain descriptors. Descriptor 1A generated an interrupt to theIntel ® 80200 processor, while descriptor 2A did not because the Interrupt Enable bit was clear.10-14 Developer’s Manual