13.07.2015 Views

Intel 80312 I/O Companion Chip - ECEE

Intel 80312 I/O Companion Chip - ECEE

Intel 80312 I/O Companion Chip - ECEE

SHOW MORE
SHOW LESS
  • No tags were found...

Create successful ePaper yourself

Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.

<strong>Intel</strong> ® <strong>80312</strong> I/O <strong>Companion</strong> <strong>Chip</strong>PCI Address Translation UnitEach ATU has a window dedicated to the following outbound PCI transaction types:• Memory reads and writes - Memory Window• I/O reads and writes - I/O Window• Dual Address Cycle reads and writes - DAC WindowRefer to Figure 5-6 for the sub-window addresses involved in primary and secondary outboundtranslation.The windowing scheme refers to:• a<strong>Intel</strong> ® 80200 processor read cycle that addresses a Memory Window is translated to aMemory Read on the PCI bus• a<strong>Intel</strong> ® 80200 processor write cycle that addresses a Memory Window is translated to aMemory Write on the PCI bus• a<strong>Intel</strong> ® 80200 processor read cycle that addresses the I/O Window is an I/O Read on the PCIbus• a<strong>Intel</strong> ® 80200 processor write cycle that addresses the I/O Window is an I/O Write on the PCIbus• a<strong>Intel</strong> ® 80200 processor read cycle that addresses a DAC Window is translated to a DACMemory Read on the PCI bus• a<strong>Intel</strong> ® 80200 processor write cycle that addresses a DAC Window is translated to a DACMemory Write on the PCI busMemory Write and Invalidate (MWI), Memory Read Line, and Memory Read Multiple commandsare not supported in outbound ATU transactions on the PCI interface.5-16 Developer’s Manual

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!