Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.11 Error ConditionsPCI provides an extensive error reporting mechanism. The PCI-to-PCI bridge implements paritygeneration and parity error detection on both the Primary and Secondary PCI interfaces and passesthat information to the Primary interface. This enables the parity error recovery mechanismsoutlined on the PCI Local Bus Specification, Revision 2.2 without special considerations for abridge.The following sections detail the bridge response to parity errors on the Primary and SecondaryPCI interfaces.4.11.1 Address Parity ErrorsThe bridge must detect and report address parity errors for transactions on both interfaces. Whenthe bridge, as a device on the initiating interface, detects an address parity error before claiming acycle, the bridge will not claim the cycle (not assert DEVSEL#) and allow the transaction toterminate with the Master-Abort mechanism.When the bridge detects an address parity error during a transaction the Primary and Secondaryinterfaces will handle the error in different manners.4.11.1.1 Address Parity Errors on Primary InterfaceWhen an address parity error occurs on the Primary interface of the bridge unit, the Intel ® 80312I/O companion chip performs the following actions based on the constraints specified:• When the Primary Parity Error Response Enable bit in the PCR is set, the Primary bridgeinterface will not claim the transaction by not asserting P_DEVSEL#, allowing a master abortto occur.When the Primary Parity Error Response Enable bit in the PCR is cleared, the Primarybridge interface takes normal action and allows the transaction to proceed (claim thetransaction when the address is within the bridge address space).• Assert P_SERR# on the Primary interface when the SERR# Enable bit and Primary ParityError Response Enable bit in the PCR are both set.• Set the Signaled System Error bit in the PSR when the SERR# Enable bit and Primary ParityError Response Enable bit in the PCR are both set. When the Signaled System Error bit in thePSR is set and the P_SERR# Asserted Interrupt Mask is clear in the SDER, set the P_SERR#Asserted bit in the PBISR• Set the Detected Parity Error bit in the PSR. When the Detected Parity Error bit in the PSR isset and the Primary Detected Parity Error Interrupt Mask bit in the SDER is clear, set DetectedParity Error bit in the PBISR.4-66 Developer’s Manual