Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPerformance Monitoring Unit11.3.2.3 M1_bridge_acqThis duration event counts the number of clocks spent by the bridge acquiring the PCI interface.The counter increments on every clock cycle after the bridge requests the PCI bus but has notactively driven the PCI bus as a master. The counter also increments for all clock cycles when thisagent’s Request Signal is asserted but bus ownership currently belongs to another master. This is anevent primitive, used in conjunction with another event primitive (number of grants granted tobridge) to calculate the average acquisition latency for the bridge.11.3.2.4 M1_bridge_ownThis duration event counts the duration for which the bridge is the master on the PCI interface. Thecounter increments on every clock cycle during which the bridge is the bus master.11.3.2.5 M1_DMA0_acqThis duration event counts the number of clocks spent by the DMA Ch-0 acquiring the PCIinterface. The counter increments on every clock cycle after the channel requests the PCI bus buthas not actively driven the PCI bus as a master. The counter also increments for all clock cycleswhen this agent’s Request Signal is asserted but bus ownership currently belongs to another master.This is an event primitive, used in conjunction with another event primitive (number of grantsgranted to DMA Ch-0) to calculate the average acquisition latency for the channel.11.3.2.6 M1_DMA0_ownThis duration event counts the duration for which DMA Ch-0 is the master on the PCI interface.The counter increments on every clock cycle during which the channel is the bus master.11.3.2.7 M1_DMA1_acqThis duration event counts the number of clocks spent by the DMA Ch-1 acquiring the PCIinterface. The counter increments on every clock cycle after the channel requests the PCI bus buthas not actively driven the PCI bus as a master. The counter also increments for all clock cycleswhen this agent’s Request Signal is asserted but bus ownership currently belongs to another master.This is an event primitive, used in conjunction with another event primitive (number of grantsgranted to DMA Ch-1) to calculate the average acquisition latency for the channel.11.3.2.8 M1_DMA1_ownThis duration event counts the duration for which DMA Ch-1 is the master on the PCI interface.The counter increments on every clock cycle during which the channel is the bus master.11.3.2.9 M1_PATU_acqThis duration event counts the number of clocks spent by the PATU acquiring the PCI interface.The counter increments on every clock cycle after the unit requests the PCI bus but has not activelydriven the PCI bus as a master. The counter also increments for all clock cycles when this agent’sRequest Signal is asserted but bus ownership currently belongs to another master. This is an eventprimitive, used in conjunction with another event primitive (number of grants granted to PATU) tocalculate the average acquisition latency for the unit.Developer’s Manual 11-7