Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPeripheral Memory-Mapped RegistersA.4 Peripheral Memory-Mapped Register AddressSpaceThe PMMR address space is divided to support the integrated peripherals on the Intel ® 80312 I/Ocompanion chip. Table A-1 shows all of the Intel ® 80312 I/O companion chip integrated peripheralmemory-mapped registers and their internal bus addresses.Table A-1. Intel ® 80200 Processor Local Addresses Assigned to Integrated PeripheralsIntegrated PeripheralPCI to PCI Bridge UnitPerformance Monitoring UnitAddress Translation UnitMessaging UnitDMA ControllerMemory ControllerInternal Arbitration UnitBus Interface UnitI 2 C Bus Interface UnitPCI And Peripheral Interrupt ControllerApplication Accelerator UnitInternal Address Block0000 1000H through 0000 10FFH0000 1100H through 0000 11FFH0000 1200H through 0000 12FFH0000 1300H through 0000 13FFH0000 1400H through 0000 14FFH0000 1500H through 0000 15FFH0000 1600H through 0000 163FH0000 1640H through 0000 167FH0000 1680H through 0000 16FFH0000 1700H through 0000 17FFH0000 1800H through 0000 18FFHThe registers accessible via PCI configuration transactions are:• PCI-to-PCI Bridge Unit• Address Translation UnitsThe registers which must have the address translation logic configured to translate PCI addressesinto the Intel ® 80200 processor address space, to access the memory-mapped registers are:• DMA Controllers• Bus Interface Unit• Memory Controller• I 2 C Bus Interface Unit• Messaging Unit• Application Accelerator Unit• Internal Arbitration Unit• Performance Monitoring• PCI and Peripheral Interrupt ControllerA-4 Developer’s Manual