Intel 80312 I/O Companion Chip - ECEE

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Intel ® 80312 I/O Companion ChipMessaging Unit6.8.19 Index Address Register - IARThe Index Address Register (IAR) contains the offset of the least recently accessed Index Register.It is written by the MU when the Index Registers are written by a PCI agent. The register is notupdated until the Index Interrupt bit in the Inbound Interrupt Status Register is cleared.The local memory address of the Index Register least recently accessed is computed by adding theIndex Address Register to the Primary Inbound ATU Translate Value Register.Table 6-25.Index Address Register - IAR3128 24 20 16 12 8 4 0PCI IOPAttributes AttributesrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrororororororororororororororororororororvrvrvrvIARIntel ® 80200 Processor Local Bus Address1380HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description31:12 000000H ReservedIndex Address - is the local memory offset of the Index Register written (050H to11:02 00H 00 2 FFCH)01:00 00 2 Reserved6.9 Power/Default StatusSoftware is responsible for initializing the Circular Queue Size in the MU Configuration Registerand all head and tail pointer registers before setting the Circular Queue Enable bit.6-36 Developer’s Manual
Intel ® 80312 I/O Companion ChipArbitration 7This chapter describes the components which comprise Intel ® 80312 I/O companion chiparbitration, which include two PCI Bus Arbiters, one PCI Selector, and two Latency Timers. Theoperation modes, setup, and implementation of these components are described in this chapter.7.1 Arbitration OverviewThe Intel ® 80312 I/O companion chip interfaces two PCI buses and contains an internal PCI-likebus. Therefore, there are three PCI buses which need an arbitration mechanism. In addition, theIntel ® 80312 I/O companion chip contains a secondary PCI arbiter for arbitrating multiple agentson the secondary PCI bus. Figure 7-1 illustrates all the potential PCI bus masters and whicharbitration components are responsible for them.Figure 7-1.Intel ® 80312 I/O Companion Chip Arbitration Block DiagramCIUAAUPCI Bus Arbiter(IARB)MLTInternal BusPATUDMA0DAM1MUSATUDMA2Primary PCI BusBDGSecondary PCI BusP_REQ#/P_GNT#PCI Selector(PSEL)ConfigurationRegistersMLTMLTPCI Bus Arbiter(SARB)S_REQ#(5:0)S_GNT#(5:0)A8295-01Developer’s Manual 7-1
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Intel 80312 I/O Companion Chip - ECEE

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