Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.7.40 Secondary ATU Command Register - SATUCMDSecondary ATU Command Register bits adhere to the definitions in the PCI Local BusSpecification, Revision 2.2 and in most cases affect the behavior of the device on the secondaryPCI bus.Table 5-68.Secondary ATU Command Register - SATUCMD15 12 840IOPAttributesrvrvrvrvrvrvrw rwrorwrorwrorw rwroPCIAttributesrvrvrvrvrvrvrw rwrorwrorwrorw rwroIntel ® 80200 Processor Local Bus Address1298HPCI Configuration Address Offset98H - 99HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description15:10 00H ReservedFast Back to Back Enable - When this bit is cleared, the secondary ATU interface is not allowed to09 0 2 generate fast back-to-back cycles on its bus.S_SERR# Enable - When this bit is cleared, the secondary ATU interface is not allowed to assert08 0 2 S_SERR# on the PCI interface.07 0 2 Wait Cycle Control - controls address/data stepping. Not implemented and a reserved bit fieldParity Error Response - When this bit is set, the secondary ATU and DMA channel 2 must take normal06 0 2 action when a parity error is detected. When it is cleared, parity checking is disabled.VGA Palette Snoop Enable - The secondary ATU interface does not support I/O writes and therefore,05 0 2 does not perform VGA palette snooping.Memory Write and Invalidate Enable - When this bit is set, DMA channel 2 may generate MWI04 0 2 commands. When this bit is clear, DMA channel 2 must use Memory Write commands instead of MWI.Special Cycle Enable - The ATU interface does not respond to special cycle commands in any way. Not03 0 2 implementedandareservedbitfield02 0 2Bus Master Enable - The secondary ATU interface has the ability to act as a master on the PCI bus. Avalue of 0 disables the secondary ATU from claiming Intel ® 80200 processor accesses and fromgenerating PCI accesses. A value of 1 allows the secondary ATU to claim Intel ® 80200 processoraccesses and to behave as a PCI bus master.This enable bit also controls the master interface of the DMA channel 2. The bit must be set beforeinitiating an DMA transfer on the PCI bus.Memory Enable - Controls the secondary ATU interface’s response to PCI memory addresses. When01 0 2 this bit is cleared, the ATU interface does not respond to any memory access on the PCI bus.I/O Space Enable - Controls the ATU interface response to I/O transactions on the primary side. Not00 0 2 implemented and a reserved bit field.5-104 Developer’s Manual