Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipClocking, Reset, and InitializationRegion 2 also contains an output clock (SCL) usedfortheI 2 C bus interface (see Chapter 12, “I 2 CBus Interface Unit”). The SCL clock frequency for I 2 C operation is 100KHz or 400KHz. SCL isgenerated from the internal bus clock. In order to use the I 2 C interface, a clock divider value mustbe written into the I 2 C Clock Count Register.15.1.4 Clocking Region 3Region 3 obtains its input clock from the clocking unit specified in clocking region 1. This regionis the Core Interface Unit. It supports clock frequencies up to a maximum of 100 MHz operation.The region 3 clock is a 3x multiple of the P_CLK.15.1.5 Clocking Region 4From clocking region 1, the Intel ® 80312 I/O companion chip generates output clock signalsS_CLK[5:0] for the secondary PCI bus devices and for clocking region 4. The Intel ® 80312 I/Ocompanion chip divides the clocking region 1 frequency by two to generate the secondary busclock outputs whenever clocking region 1 is operating at 66 MHz and clocking region 4 isoperating at 33 MHz. The Intel ® 80312 I/O companion chip selects the proper clocking region1/clocking region 4 frequency combination by sampling the 66 MHz enables pins, P_M66EN andS_M66EN during PCI reset.In order to satisfy PCI interface timings, the secondary PCI bus interface of the Intel ® 80312 I/Ocompanion chip needs to be skew matched with the external secondary PCI bus agents. Toaccomplish this, the Intel ® 80312 I/O companion chip provides output and input reference clockpins. The R_CLKOUT pin should be routed out and back to the R_CLKIN pin via a trace that isskew matched to S_CLK[5:0].Note:The frequency of the R_CLKOUT output pin tracks the P_CLK input pin’s frequency.The Intel ® 80312 I/O companion chip clocking hardware does not support a 33 MHz clockingregion 1 along with a 66 MHz clocking region 4.15.1.6 Output ClocksTable 15-1 shows the loading requirements for each of the output clocks. Refer to the SDRAMSpecification (4-clock 66Mhz, 64-bit unbuffered SDRAM DIMM Specification) for the clockskew and loading requirements for the SDRAM devices. Refer to the PCI Local Bus Specification,Revision 2.2 for details on PCI bus clock loading requirements.Table 15-1.Output Clocks Loading SummaryPin Minimum MaximumDCLK[3:0] 22 pF + Trace 38 pF + TraceDCLKOUT 22 pF + Trace 38 pF + TraceSCL tbd pF + Trace tbd pF + TraceS_CLK[5:0] tbd pF + Trace tbd pF + TraceR_CLKOUT tbd pF + Trace tbd pF + TraceDeveloper’s Manual 15-3