Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipMemory Controller3.3 Power Failure ModeThe Intel ® 80312 I/O companion chip is an I/O processor used in server applications includingnetworking and storage. Specifically, the storage applications supported utilize the Intel ® 80312I/O companion chip as the IOP for a SCSI RAID disk subsystem. The integrated memorycontroller supports up to 512 Mbytes of local memory used for disk caching. The local memory isused for the temporary storage of disk writes which greatly improves disk performance.For the Intel ® 80312 I/O companion chip memory controller, up to 512 Mbytes may be storedwithin the disk cache. While the host assumes all written data is stored on the non-volatile disksubsystem, the IOP must ensure that eventually all the data in the disk cache is actually stored ontodisk.The power supply could fail to provide power to the I/O subsystem in the case of a power outage ora failed power supply. It is imperative that the cached data within the IOP local memory is not lost.When power fails, the local memory subsystem must remain powered with a battery backup andsome agent must continue to refresh at the appropriate interval specified by the memorycomponent datasheet.This proposal defines the mechanism which the Intel ® 80312 I/O companion chip’s memorycontroller ensures that the data within local memory is not lost during a power failure.3.3.1 Theory of OperationSDRAM technology provides a simple way of enabling data preservation through the self-refreshcommand. This command is issued by the memory controller and the SDRAM refreshes itselfautonomously with internal logic and timers. The self-refresh command is defined in Table 3-12.The SDRAM device remains in self-refresh mode as long as:• Thedevicecontinuestobepowered.• SCKE is held low until the memory controller is ready to control the SDRAM once again.Power to the SDRAM subsystem is ensured with an adequate battery backup and a reliable methodfor switching between system power and battery power. The memory controller is responsible fordeasserting SCKE[1:0] when issuing the self-refresh command but while power gradually drops,SCKE[1:0] MUST remain deasserted regardless of the state of V cc powering the Intel ® 80312 I/Ocompanion chip.Developer’s Manual 3-35