Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipIntel ® 80200 Processor based on Intel ® XScale Microarchitecture Core Interface Unit8.5 Data TransfersThe read transactions generated by the Intel ® 80200 processor requires either one or four dataphases. The write transactions can have either one or two data phases.8.5.1 Intel ® 80200 Processor Request Bus Read from SDRAMThe Intel ® 80200 processor request bus issues a read command for 8 bytes of data from SDRAMcontrolled by the MCU.1. On the rising-edge of clock 1,the Intel ® 80200 processor asserts active low ADS# to indicate avalid request bus command. The Intel ® 80200 processor (for read) asserts active low W/R#.The LOCK# signal is deasserted indicating that the read is not initiating a locked atomic readmodify write operation. Also on the first rising edge, the Intel ® 80200 processor asserts themost significant 16 bits of address on ADD[15:0]. This address is translated by the CIU tointernal bus address bits [31:16] (I_AD[31:16]).2. On the rising edge of clock 2, the Intel ® 80200 processor asserts the request transfer length(LEN[2:0]) onADS#, W/R# and LOCK#. The least significant 16 bits of address are drivenon ADD[15:0]. This address is translated by the CIU to internal bus address bits [15:0](I_AD[15:0]).3. The CIU issues a request for ownership of the internal PCI bus to the arbiter.4. The Arbiter grants ownership of the internal bus to the CIU.5. The CIU asserts the C_HOLDMCU sideband signal to obtain ownership of the SDRAM bus.6. The MCU acknowledges that it is ready to perform the CIU transaction by asserting theM_HOLDACK sideband signal.7. The CIU asserts frame on the internal bus (I_FRAME#) and supplies the appropriate PCIcommand - “memory read” for a transaction of less than 8 bytes, “memory read line” for an 8byte transaction, and “memory read multiple” for requests greater than 8 bytes.8. The CIU asserts the internal bus I_IRDY# signal indicating that as initiator it is ready toreceive data.9. The MCU claims the internal bus transaction by asserting I_DEVSEL#.10. The MCU provides row and column address for the SDRAM.11. The MCU asserts the M_DVALID sideband signal to indicate to the CIU that the SDRAMbegins transferring the requested burst data in 3 clock cycles. The SDRAM timing, and theassociated M_DVALID signal timing are dependent on whether the requested memory accessisapagehitorpagemiss.12. The CIU asserts the Intel ® 80200 processor request bus C_DVALID signal to indicate thatdata transferred on DQ[63:0] and check bits transferred on SCB[7:0] are valid in two clockcycles. C_DVALID is asserted for one clock period for each cycle of data to be transferred inthe burst.13. The Intel ® 80200 processor registers the read data and check bits. Error detection andcorrectionisdisabledintheMCU.IfasinglebiterrorisdetectedbytheIntel ® 80200processor the processor’s internal error correction logic inverts the offending bit. Multiple biterrorsarealsodetectedinternallybytheIntel ® 80200 processor during reads from SDRAMvia the MCU.8-6 Developer’s Manual