Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipMemory ControllerOpen pages allow optimal performance when a read or write occurs to an open page. Multiple openpages allow multiple memory segments to be open simultaneously and is well-suited for the Intel ®80312 I/O companion chip’s system environment. The MCUs paging algorithm is detailed inSection 3.2.3.3, “Page Hit/Miss Determination” on page 3-16. The waveforms illustrating theperformance issues are in Section 3.2.3.7, “SDRAM Read Cycle” on page 3-21 andSection 3.2.3.8, “SDRAM Write Cycle” on page 3-24.Figure 3-6 illustrates how two banks of SDRAM would interface with the Intel ® 80312 I/Ocompanion chip through the MCU.Figure 3-6.Dual-Bank SDRAM Memory SubsystemIntel ® 80312I/O CompanionChipDQ[63:0]SC[7:0]SRAS#SCAS#SWE#SA[12:0]SBA[1:0]SDQM[7:0]SCKESCE0SCE1DQ[63:0]CB[7:0]RAS#CAS#WE#A[12:0]BA[1:0]DQM[7:0]CKE[1:0]CS[3:0]#SDRAM DIMMDQ[63:0]CB[7:0]RAS#CAS#WE#A[12:0]BA[1:0]DQM[7:0]CKE[1:0]CS[3:0]#SDRAM DIMMA8266-013-12 Developer’s Manual