Intel 80312 I/O Companion Chip - ECEE

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Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.7.9 ATU Header Type Register - ATUHTRHeader Type Register bit definitions adhere to PCI Local Bus Specification, Revision 2.2. Thisregister indicates the layout of ATU and Messaging Unit register configuration space bytes 10H to3FH. The MSB indicates whether or not the device is multi-function. (Refer to Section 5.2.4, “PCIMulti-Function Device Swapping/Disabling” on page 5-24 for using this register in other than itsdefault state.)Table 5-36.ATU Header Type Register - ATUHTRIOPAttributes7 4 0rw rw rw rw rw rw rw rwPCIAttributesrorororororororoIntel ® 80200 Processor Local Bus Address120EHPCI Configuration Address Offset0EHAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description07 1 2 Single Function/Multi-Function Device - Identifies the ATU as a multi-function PCI device.PCI Header Type - This bit field indicates the type of PCI header implemented. The ATU interface06:00 000000 2 header conforms to PCI Local Bus Specification, Revision 2.2.5-70 Developer’s Manual
Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.7.10 Primary Inbound ATU Base Address Register - PIABARThe Primary Inbound ATU Base Address Register (PIABAR) defines the block of memoryaddresses where the primary inbound translation window begins. The inbound ATU decodes andforwards the bus request to the Intel ® 80312 I/O companion chip internal bus with a translatedaddress to map into Intel ® 80312 I/O companion chip local memory. The PIABAR defines the baseaddress and describes the required memory block size; see Section 5.7.15, “Determining BlockSizes for Base Address Registers” on page 5-76. Bits 31 through 12 of the PIABAR is eitherread/write bits or read only with a value of 0 depending on the value located within the PIALR.This configuration allows the PIABAR to be programmed per PCI Local Bus Specification,Revision 2.2.The first 4 Kbytes of memory defined by the PIABAR and the PIALR is reserved for theMessaging Unit.The programmed value within the base address register must comply with the PCI programmingrequirements for address alignment. Refer to the PCI Local Bus Specification, Revision 2.2 foradditional information on programming base address registers.Table 5-37.Primary Inbound ATU Base Address Register - PIABARIOPAttributes31 28 24 20 16 12 8 4 0rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rv rv rv rv rv rv rv rv ro ro ro roPCIAttributesrwrw rw rw rw rw rw rwrw rw rw rw rw rw rw rwrw rw rw rwrvrvrvrvrvrvrvrvrorororoIntel ® 80200 Processor Local Bus Address1210HPCI Configuration Address Offset10H - 13HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description31:12 00000HPrimary Translation Base Address - These bits define the actual location the Primary translation functionis to respond to when addressed from the PCI bus. The default base address is undefined.11:04 00H Reserved.03 1 2 Prefetchable Indicator - Defines the memory spaces as prefetchable.Address Type - These bits define where the block of memory can be located. The base address must be02:01 00 2 locatedanywhereinthefirst4Gbyteofaddressspace(lower32bitsofaddress).Memory Space Indicator - This bit field describes memory or I/O space base address. The primary ATU00 0 2 does not occupy I/O space, thus this bit must be zero.Developer’s Manual 5-71
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Intel ® 80200 Processor based on I
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