Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.6.6.4 Memory Write and Invalidate CommandThe Memory Write and Invalidate (MWI) command is essentially identical to the Memory Writecommand except it guarantees a minimum transfer of at least one cacheline as defined by theCacheline Size Register (CLSR). The initiating PCI master will only allow the transaction to crossthe predefined cacheline boundary when it intends to transfer the entire next cacheline.The target interface of the bridge must guarantee that there is enough free queue space in the PMWdata queue to accept an MWI transaction. When this is not true, the MWI is retried. Once a fullcacheline is accepted and the master continues bursting into the next cacheline, this decision needsto be made again and so on. For example, when in the upstream queue, an MWI is active on theSecondary bus, a full cacheline (32 bytes in this case) has already been transferred, and theU_PMWD queue only has 24 free bytes available, the Secondary interface of the bridge willperform a disconnect without data on the first data phase of the next cacheline. When U_PMWDqueue, in this case, had 32 bytes or more of free queue space available, the Secondary interfacewould continue accepting the next cacheline.When the bridge accepts an MWI command which is terminated with a Master Abort on the targetbus, the bridge may disconnect the transaction before transferring an entire cacheline into thequeue.When the bridge accepts an MWI command which is terminated by the master before the entirecacheline is transferred, the bridge will complete the transaction using a Memory Write Invalidatecommand to transfer the partial cacheline.When the bridge accepts an MWI command which is disconnected by the target (on the targetinterface) before the entire cacheline is transferred, the bridge will complete the transaction using aMemory Write command to transfer the partial cacheline. When the transaction is still in progress(streaming), the bridge is free to disconnect the initiator with a target disconnect on the initiatingbus in the middle of a cacheline. No other action is taken by the bridge unit; no error is reported.To satisfy the MWI command protocol, the target interface of the bridge will deassert IRDY#(master wait state) when a stream is occurring (data transferred on initiating and target interfacesimultaneously) and the target interface is capable of a faster transfer rate than the initiatinginterface. This can occur due to varying bus or target widths or bus speeds or master wait statesfrom the initiator on the initiating bus. (Master wait states may cause the bridge to insert more than8 IRDY# wait-states between data phases on the target bus.)The bridge unit converts a MWI command to a Memory Write command when the CLSR isprogrammedtoavalueofzeroorwhentheCachelineSizeRegisterisprogrammedtoavalueotherthan 8 or 16. Refer to the PCI Local Bus Specification, Revision 2.2 for the full details of aMemory Write and Invalidate command.When posting is disabled, the bridge will not allow the MWI command to appear on the target bus.The bridge will convert the MWI to a Memory Write and only allow one PCI data phase on thetarget bus.When the MWI Alias bit is set in the Queue Control Register, the bridge will accept an MWIcommand as long as the PMW queue is not in a full state. This means that there does not need to beat least a cacheline of queue space free to accept the MWI. When the MWI Alias bit is set, thebridge target interface will alias the MWI command to a Memory Write command for transfer to thePCI target. MWI master rules do not apply. In addition, MWI transactions which start on anon-cacheline boundary are treated as when the MWI alias bit is set, i.e. they are aliased to anMemory Write.Developer’s Manual 4-45