Intel 80312 I/O Companion Chip - ECEE

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Intel ® 80312 I/O Companion ChipPCI Address Translation UnitTable 5-26. Address Translation Unit Registers (Sheet 2 of 2)Register NameBitsPCIConfigurationCycleRegisterNumberLocal BusAddressATU Configuration Register - ATUCR 32 34 0000.1288HPrimary ATU Interrupt Status Register - PATUISR 32 36 0000.1290HSecondary ATU Interrupt Status Register - SATUISR 32 37 0000.1294HSecondary ATU Command Register - SATUCMD 16 38 0000.1298HSecondary ATU Status Register - SATUSR 16 38 0000.129AHSecondary Outbound DAC Window Value Register - SODWVR 32 39 0000.129CHSecondary Outbound Upper 64-bit DAC Register - SOUDR 32 40 0000.12A0HPrimary Outbound Configuration Cycle Address Register - POCCAR 32 41 0000.12A4HSecondary Outbound Configuration Cycle Address Register - SOCCAR 32 42 0000.12A8HPrimary Outbound Configuration Cycle Data Register - POCCDR 32Secondary Outbound Configuration Cycle Data Register - SOCCDR 32Not Available inPCI ConfigurationSpaceNot Available inPCI ConfigurationSpace0000.12ACH0000.12B0HPrimary ATU Queue Control Register - PAQCR 32 45 0000.12B4HSecondary ATU Queue Control Register - SAQCR 32 46 0000.12B8HPrimary ATU Interrupt Mask Register - PATUIMR 32 47 0000.12BCHSecondary ATU Interrupt Mask Register - SATUIMR 32 48 0000.12C0H5-58 Developer’s Manual
Intel ® 80312 I/O Companion ChipPCI Address Translation UnitTable 5-27. ATU PCI Configuration Register Space (Sheet 1 of 2)LocalBusAddressOffsetATU PCI Configuration Register Section, Name, Page00H Section 5.7.1, “ATU Vendor ID Register - ATUVID” on page 5-6102H Section 5.7.2, “ATUDeviceIDRegister-ATUDID” on page 5-6204H Section 5.7.3, “Primary ATU Command Register - PATUCMD” on page 5-6306H Section 5.7.4, “Primary ATU Status Register - PATUSR” on page 5-6408H Section 5.7.5, “ATU Revision ID Register - ATURID” on page 5-6609H Section 5.7.6, “ATU Class Code Register - ATUCCR” on page 5-670CH Section 5.7.7, “ATU Cacheline Size Register - ATUCLSR” on page 5-680DH Section 5.7.8, “ATU Latency Timer Register - ATULT” on page 5-690EH Section 5.7.9, “ATU Header Type Register - ATUHTR” on page 5-7010H Section 5.7.10, “Primary Inbound ATU Base Address Register - PIABAR” on page 5-712CH Section 5.7.11, “ATU Subsystem Vendor ID Register - ASVIR” on page 5-722EH Section 5.7.12, “ATU Subsystem ID Register - ASIR” on page 5-7330H Section 5.7.13, “Expansion ROM Base Address Register - ERBAR” on page 5-7434H Section 5.7.14, “ATU Capabilities Pointer Register - ATU_Cap_Ptr” on page 5-753CH Section 5.7.16, “ATU Interrupt Line Register - ATUILR” on page 5-773DH Section 5.7.17, “ATU Interrupt Pin Register - ATUIPR” on page 5-783EH Section 5.7.18, “ATU Minimum Grant Register - ATUMGNT” on page 5-793FH Section 5.7.19, “ATU Maximum Latency Register - ATUMLAT” on page 5-8040H Section 5.7.20, “Primary Inbound ATU Limit Register - PIALR” on page 5-8144H Section 5.7.21, “Primary Inbound ATU Translate Value Register - PIATVR” on page 5-8248H Section 5.7.22, “Secondary Inbound ATU Base Address Register - SIABAR” on page 5-834CH Section 5.7.23, “Secondary Inbound ATU Limit Register - SIALR” on page 5-8450H Section 5.7.24, “Secondary Inbound ATU Translate Value Register - SIATVR” on page 5-8554H Section 5.7.25, “Primary Outbound Memory Window Value Register - POMWVR” on page 5-865CH Section 5.7.26, “Primary Outbound I/O Window Value Register - POIOWVR” on page 5-8760H Section 5.7.27, “Primary Outbound DAC Window Value Register - PODWVR” on page 5-8864H Section 5.7.28, “Primary Outbound Upper 64-bit DAC Register - POUDR” on page 5-8968H Section 5.7.29, “Secondary Outbound Memory Window Value Register - SOMWVR” on page 5-906CH Section 5.7.30, “Secondary Outbound I/O Window Value Register - SOIOWVR” on page 5-9174H Section 5.7.31, “Expansion ROM Limit Register - ERLR” on page 5-9278H Section 5.7.32, “Expansion ROM Translate Value Register - ERTVR” on page 5-9380H Section 5.7.33, “ATU_Capability Identifier Register - ATU_Cap_ID” on page 5-9481H Section 5.7.34, “ATU Next Item Pointer Register - ATU_Next_Item_Ptr” on page 5-9582H Section 5.7.35, “ATU Power Management Capabilities Register - APMCR” on page 5-9684H Section 5.7.36, “ATU Power Management Control/Status Register - APMCSR” on page 5-9788H Section 5.7.37, “ATU Configuration Register - ATUCR” on page 5-98Developer’s Manual 5-59
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PCI and Peripheral Interrupt Contro
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Memory Controller 3This chapter des
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Messaging Unit 6This chapter descri
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DMA Controller Unit 9This chapter d
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Application Accelerator Unit 10This
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General Purpose Input Output (GPIO)
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Intel 80312 I/O Companion Chip - ECEE

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