Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.7.31 Expansion ROM Limit Register - ERLRThe Expansion ROM Limit Register (ERLR) defines the block size of addresses the primary ATUdefines as Expansion ROM address space. The block size is programmed by writing a value intothe ERLR from the Intel ® 80200 processor.Bits 31 to 12 within the ERLR have a direct effect on the ERBAR register, bits 31 to 12, with a oneto one correspondence. A value of 0 in a bit within the ERLR makes the corresponding bit withinthe ERBAR a read only bit which always returns 0. A value of 1 in a bit within the ERLR makesthe corresponding bit within the ERBAR read/write from PCI.Table 5-59.Expansion ROM Limit Register - ERLRIOPAttributes31 28 24 20 16 12 8 4 0rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rv rv rv rv rv rv rv rv rv rv rv rvPCIAttributesrw rw rw rw rw rw rw rwrw rw rw rw rw rw rw rwrw rw rw rwrvrvrvrvrvrvrvrvrvrvrvrvIntel ® 80200 Processor Local Bus Address1274HPCI Configuration Address Offset74H - 77HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description31:12 000000HExpansion ROM Limit - Block size of memory required for the Expansion ROM translation unit. Defaultvalue is 0, which indicates no Expansion ROM address space and all bits within the ERBAR are readonly with a value of 0.11:00 000H Reserved5-92 Developer’s Manual