Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.11.2.2 Delayed Write Data ParityTo allow for correct data parity calculations for delayed write transactions, the bridge will delay theassertion of STOP# (signalling a Retry) until PAR is driven by the master. A parity error during adelayed write transaction can occur in any of the following parts of the transactions:• During the Delayed Write Request cycle on the initiating bus when the transaction is enqueuedby the bridge unit.• During the Delayed Write Completion cycle on the target bus when the write data is deliveredto the target and write status is capture for delivery to the initiator• During the Delayed Write Completion cycle on the initiating bus when write status is to bedelivered to the initiator who has retried the transaction.Depending on where and when the parity error occurs, different responses are required.The Intel ® 80312 I/O companion chip Primary bridge interface has the following responses to adelayed write parity error for downstream transactions during Delayed Write Request cycles on theinitiating bus with the given constraints:• When the Primary Parity Error Response bit in the PCR is set, the Primary bridge interfaceasserts P_TRDY# (disconnects with data) and two clock cycles later asserts P_PERR#notifying the initiator of the parity error. The delayed write cycle in not enqueued and notforwarded to the Secondary interface.The Detected Parity Error bit is set in the Primary Status Register (PSR) only when datahas been transferred. This scenario would occur when a request is seen with bad parity. Inthis case the request is immediately completed and discarded. Because of the completion,data has been transferred on the initiating interface. When the Primary Detected ParityError Interrupt Mask bit is clear in the SDER, set the Detected Parity Error bit in thePBISR.• When the Primary Parity Error Response bit in the PCR is cleared, the Primary bridgeinterface retries the transaction by asserting P_STOP# and enqueues the Delayed WriteRequest cycle to be forwarded to the Secondary bridge interface. P_PERR# is not asserted.On the Secondary bridge interface, the following responses to a delayed write parity error forupstream transactions during Delayed Write Request cycles on the initiating bus with the givenconstraints:• When the Secondary Parity Error Response bit in the BCR is set, the Secondary bridgeinterface asserts S_TRDY# (disconnecting with data) and two clock cycles later assertsS_PERR# notifying the initiator of the parity error. The delayed write cycle in not enqueuedand not forwarded to the Primary interface.The Detected Parity Error bit is set in the Secondary Status Register (SSR) only when datahas been transferred. This scenario would occur when a request is seen with bad parity. Inthis case the request is immediately completed and discarded. Because of the completion,data has been transferred on the initiating interface. When the Secondary Detected ParityError Interrupt Mask bit is clear in the SDER, set the Detected Parity Error bit in theSBISR.• When the Secondary Parity Error Response bit in the BCR is cleared, the Secondary bridgeinterface retries the transaction by asserting S_STOP# and enqueues the Delayed WriteRequest cycle to be forwarded to the Primary bridge interface. S_PERR# is not asserted.Developer’s Manual 4-69