Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.7.37 ATU Configuration Register - ATUCRThe ATU Configuration Register controls the outbound address translation for both the primaryand secondary outbound translation units. It also contains bits for DRC aliasing, discard timerstatus, P_SERR# and S_SERR# manual assertion, access to the messaging unit from the secondaryPCI bus, and P_SERR# and S_SERR# detection interrupt masking.Table 5-65. ATU Configuration Register - ATUCR (Sheet 1 of 2)IOPAttributesrv31rvrv28 24 20 16 12 8 4 0rv rv rv rv rv rv rv rw rw rw rw rw rw rc rv rv rw rv rw rw rw rw rv rv rv rv rw rw rvPCIAttributesrvrvrvrvrvrvrvrvrvrvrorw rw rw rw rwrcrvrvrwrvrw rw rw rwrvrvrvrvrw rwrvIntel ® 80200 Processor Local Bus Address1288HPCI Configuration Address Offset88H - 8BHAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description31:22 00H Reserved21 0 2Bridge Function Number - this bit in conjunction with the ATU Header Type Register (ATUHTR) and theBridge Header Type Register (HTR), can swap the Bridge and the ATU device numbers as they appearto the PCI bus, or it can set the Intel ® 80312 I/O companion chip as a single function device with eitherthe ATU or the Bridge as the single function. (Refer to Section 5.2.4, “PCI Multi-Function DeviceSwapping/Disabling” on page 5-24 for programming information.)20 0 2to match a current PCI read transaction with read data enqueued within the DRC buffer. When clear, acurrent read transaction must have the exact same read command as the DRR for the secondary ATUSATU DRC Alias - when set, the secondary ATU does not distinguish read commands when attemptingto deliver DRC data.19 0 2match a current PCI read transaction with read data enqueued within the DRC buffer. When clear, acurrent read transaction must have the exact same read command as the DRR for the primary ATU toPATU DRC Alias - when set, the primary ATU does not distinguish read commands when attempting todeliver DRC data.18 0 2Direct Addressing Upper 2Gbytes Translation Enable - When set, with Direct Addressing enabled (bit 7of the ATUCR set), the ATU forwards internal bus cycles with an address between 0000.2000H and7FFF.FFFFH to the PCI bus with bit 31 of the address set (8000.2000H - FFFF.FFFFH). When clear, notranslation occurs.17 0 2S_SERR# Manual Assertion - when set, the SATU asserts S_SERR# for one clock on the secondaryPCI interface. Until cleared, S_SERR# may not be manually asserted again. Once cleared, operationproceeds as specified.16 0 2P_SERR# Manual Assertion - when set, the PATU asserts P_SERR# for one clock on the primary PCIinterface. Until cleared, P_SERR# may not be manually asserted again. Once cleared, operationproceeds as specified.15 0 2ATU Discard Timer Status - when set, one of the 3 discard timers within the PATU and SATU hasexpired and discarded the delayed completion transaction within the queue. When clear, no timer hasexpired.14:13 00 2 Reserved5-98 Developer’s Manual