Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPerformance Monitoring Unit11.6.1 Global Timer Mode Register (GTMR)The Global Timer Mode Register (GTMR) programs the mode of operation or indicates the currentmode of the Global Time Stamp Counter as shown in Table 11-5. This is a 32-bit, read-writeregister. Bit 0 controls the interrupt capability of the Global Time Stamp Counter. When enabled,an interrupt is generated to the Intel ® 80200 processor on the FIQ# interrupt pin when the GlobalTime Stamp Counter overflows. Bit 2 is an enable/disable bit. When set (1), the ProgrammableEvent Counters and the Global Time Stamp Counter are disabled and retain their previous values.This bit needs to be rewritten to enable all counters.Table 11-5.Global Timer Mode Register (GTMR)IOPAttributesrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrvrwrvrwPCIAttributesna na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na31 28 24 20 16 12 8 4 0Intel ® 80200 Processor Local Bus AddressAttribute Legend: RW = Read/Write0000 1100HRV = Reserved RC = Read ClearPR = Preserved RO = Read OnlyRS = Read/Set NA = Not AccessibleBit Default Description31:03 0 Reserved2 0 2Bit value determines when the Global Time Stamp Counter and the Programmable Event Counters areenabled or disabled.0 = All counters enabled (enable counting)1 = All counters disabled (disable counting)1 0 2 Reserved0 0 2an overflow condition.0 = Interrupt disabledBit value determines whether the Global Time Stamp Counter interrupts the Intel ® 80200 processor on1 = Interrupt enabledDeveloper’s Manual 11-23