Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipIntel ® 80200 Processor based on Intel ® XScale Microarchitecture Core Interface Unit14. Having deasserted C_DVALID and transferred the requested data to the Intel ® 80200processor, the CIU deasserts C_HOLDMCU.15. The CIU transfers and discards internal bus read data from the MCU.16. The MCU deasserts M_HOLDACK to complete the transaction.17. The CIU clears the current request register and executes the next pending request buscommand. If no requests are pending the CIU returns to the idle state where it waits for thenext Intel ® 80200 processor request.Figure 8-3 shows the described read transaction in more detail.Figure 8-3.SDRAM Dual Word Read with Page Hit1 2 3 4 5 6 7 8 9 10 11 12 13 14ADS#/len[2]LOCK#/len[1]W/R#/len[0]ADD[15:0]C_HOLDMCUM_HOLDACKC_REQA_CIUGNTI_C/BE[7:0]#I_AD[63:0]#I_FRAME#I_IRDY#I_DEVSEL#I_TRDY#I_STOP#M_DVALIDC_DVALIDM_DATE#C_DQE#DQ[63:0]SCB[7:0]A0_MSA0_LSEE 00 00 00A0D000D0 D1 D2 D3C0 C1 C2 C318. Following the Intel ® 80200 processor request, the CIU indicates that requested 8 bytes of datais valid. The memory controller continues the SDRAM access until 32 bytes of data have beenplaced on the data bus. After 8 bytes of data are transferred, the Intel ® 80200 processor mayadd another request to the queue if less than four instructions are pending. A 32 byte loadwould look very similar to the timing diagram in Figure 8-3, but would extend the dvalidassertion duration three clocks.Developer’s Manual 8-7