Intel 80312 I/O Companion Chip - ECEE

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Intel ® 80312 I/O Companion ChipApplication Accelerator Unit• The sixth word is the destination address where the XOR-ed data is stored in Intel ® 80200processor local memory. This address is driven on the internal bus. This value is loaded intothe Destination Address Register.• The seventh word is the Byte Count value. This value determines the total number of bytes ofdata to XOR in the current chain descriptor. This value is loaded into the Accelerator ByteCount Register.• The eighth word is the Descriptor Control Word. This word configures the ApplicationAccelerator for one operation. This value is loaded into the Accelerator Descriptor ControlRegister.• The ninth word (1st word of mini-descriptor) is the address of the fifth block of data resident inIntel ® 80200 processor local memory. This address is driven on the internal bus. This value isloaded into SAR5.• The tenth word (2nd word of mini-descriptor) is the address of the sixth block of data residentin Intel ® 80200 processor local memory. This address is driven on the internal bus. This valueis loaded into SAR6.• The eleventh word (3rd word of mini-descriptor) is the address of the seventh block of dataresident in Intel ® 80200 processor local memory. This address is driven on the internal bus.This value is loaded SAR7.• The twelfth word (4th word of mini-descriptor) is the address of the eighth block of dataresident in Intel ® 80200 processor local memory. This address is driven on the internal bus.This value is loaded into SAR 8.A series of chain descriptors can be built in local memory to XOR multiple blocks of source dataresident in Intel ® 80200 processor local memory. The XOR-ed result is then stored back in Intel ®80200 processor local memory. An application can build multiple chain descriptors to XOR manyblocks of data which have different source addresses within the local memory.10-8 Developer’s Manual
Intel ® 80312 I/O Companion ChipApplication Accelerator UnitWhen multiple chain descriptors are built in Intel ® 80200 processor local memory, the applicationcan link each of these chain descriptors using the Next Descriptor Address in the chain descriptor.This address logically links the chain descriptors together. This allows the application to build a listof transfers which may not require the use of the Intel ® 80200 processor until all transfers arecomplete. Figure 10-6 shows an example of a linked-list of transfers specified in external memory.Figure 10-6.XOR Chaining OperationDescriptor Address RegisterAccelerator Control RegisterLinked Descriptors In Local MemoryNext Descriptor Address (NDA)Source Address (SAR1)Source Address (SAR2)Source Address (SAR3)Source Address (SAR4)Destination Address (DAR)Byte Count (BC)Descriptor Control (DC)Source Address (SAR5)Source Address (SAR6)Source Address (SAR7)Source Address (SAR8)Buffer TransfersFirst Chain DescriptorXOROperation...Next Descriptor Address (NDA)Source Address (SAR1)Source Address (SAR2)Source Address (SAR3)Source Address (SAR4)Destination Address (DAR)Byte Count (BC)Descriptor Control (DC)Source Address (SAR5)Source Address (SAR6)Source Address (SAR7)Source Address (SAR8)End of Chain(Null Value Detected)Nth Chain DescriptorXOROperationDeveloper’s Manual 10-9
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Memory Controller 3This chapter des
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Intel ® 80200 Processor based on I
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Intel 80312 I/O Companion Chip - ECEE

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