Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.15.15 I/O Limit Register - IOLRI/O Limit Register bits adhere to the definitions in the PCI Local Bus Specification,Revision2.2.The I/O Limit Register defines the upper address (inclusive) of an address range that is used todetermine when to forward I/O transactions from one side of the bridge to the other. It must beprogrammed with a valid value greater than or equal to the IOBR before the I/O Space Enable bitin the Primary Command Register (PCR) is set. The bridge only supports 16-bit addressing whichis indicated by a value of 0H in the four least significant bits of the register. The upper 4 bits areprogrammed with AD[15:12] for the top of the address range. AD[11:0] of the limit address isalways FFFH forcing a 4 Kbyte I/O range granularity.For the purposes of address decoding, the bridge assumes that AD[31:16], the upper 16 addressbits of the I/O address, are zero. The bridge must still perform the address decode on the full 32 bitsof address per PCI Local Bus Specification, Revision 2.2 and check that the upper 16 bits are equalto 0000H.The I/O address range (defined by the IOBR in conjunction with the IOLR) is modified by the ISAEnable bit of the Bridge Control Register. When this bit is set then I/O addresses in the rangeX400H - XFFFH will not be accepted by the Primary side of the bridge, even when the addressfalls within the defined I/O address range.The VGA Enable bit in the BCR will cause I/O accesses where AD[9:0] are in the ranges3B0H - 3BBH and 3C0H - 3DFH (inclusive of ISA addresses - AD[15:10] are not decoded) to beforwarded from primary to secondary and blocked from secondary to primary.Table 4-38.I/O Limit Register - IOLRIOPAttributes7 4 0rw rw rw rw ro ro ro roPCIAttributesrw rw rw rwrorororoPCI Configuration Offset1DHIntel ® 80200 Processor Local Bus Address0000 101DHAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description07:04 0HI/O Limit Address - This field is programmed with AD[15:12] of the top of the I/O address range to bepassed down the hierarchy by the bridge.03:00 0H I/O Addressing Capability - The value of 0H signifies that the bridge only supports 16-bit I/O addressing.4-100 Developer’s Manual