Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.6.2.2 Outbound Write Data Parity Errors - MasterData parity errors occurring during write operations initiated by the ATU may record the assertionof PERR# from the target on the PCI Bus. When an error occurs, the ATUs continues writing datato the target to clear the OWQ of the current outbound write transaction. Specifically, the followingactions with the given constraints are taken on both the primary and secondary ATUs:Table 5-11.Outbound Write Data Parity Errors - MasterPrimary ATUIf P_PERR# is sampled active and the Parity ErrorResponse bit in the PATUCMD is set, set the MasterParity Error bit in the PATUSR. If the Parity ErrorResponse bit in the PATUCMD is clear, no action istaken.If the PATU PCI Master Parity Error Interrupt Mask Bitin the PATUIMR is clear, set the PCI Master ParityError bit in the PATUISR, when set, no action.Secondary ATUIf S_PERR# is sampled active and the Parity ErrorResponse bit in the SATUCMD is set, set the MasterParity Error bit in the SATUSR. If the Parity ErrorResponse bit in the SATUCMD is clear, no action istaken.If the SATU PCI Master Parity Error Interrupt Mask Bitin the SATUIMR is clear, set the PCI Master ParityErrorbitintheSATUISR,whenset,noaction.Outbound write parity errors, as stated, does not result in a master completion. In addition, whenthe target terminates the transaction (disconnect), the ATU master must reinitiate the transaction toclear the data from the OWQ.5.6.2.3 Inbound Read Data Parity Errors - SlaveInbound read data parity errors occur when read data delivered from the IRQ is detected as havingbad parity by the master of the transaction who is receiving the data. The master may optionallyreport the error to the system by asserting PERR#. As a slave device in this scenario, no action isrequired and no error bits are set.5.6.2.4 Inbound Write Data Parity Errors - SlaveData parity errors occurring during write operations received by the ATU may assert PERR# onthe PCI Bus. When an error occurs, the ATUs continues accepting data until the master of the writetransaction completes or a queue fill condition is reached. Specifically, the following actions withthe given constraints are taken on both the primary and secondary ATUs:Table 5-12.Inbound Write Data Parity Errors - SlavePrimary ATUP_PERR# is asserted two clocks cycles following thedata phase in which the data parity error is detectedon the primary bus. This is only done when the ParityError Response bit in the PATUCMD is set.The Detected Parity Error bit in the PATUSR is setIf the PATU Detected Parity Error Interrupt Mask bit inthe PATUIMR is clear, set the Detected Parity Error bitinthePATUISR.whenset,noactionSecondary ATUS_PERR# is asserted two clocks cycles following thedata phase in which the data parity error is detectedon the secondary bus. This is only done when theParity Error Response bit in the SATUCMD is set.The Detected Parity Error bit in the SATUSR is setIf the SATU Detected Parity Error Interrupt Mask bit inthe SATUIMR is clear, set the Detected Parity Error bitintheSATUISR.whenset,noaction5-42 Developer’s Manual