Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipDMA Controller Unit9.13 Power-up/Default StatusUpon power-up, an external hardware reset, the DMA Registers is initialized to their defaultvalues.9.14 Register DefinitionsThe DMA controller contains registers for controlling each channel. Each channel has ninememory-mapped control registers for independent operation. In register titles, x is 0, 1, or 2 forchannel0,1,or2respectively.There is read/write access only to the Channel Control Register, Channel Status Register, and theNext Descriptor Address Register. The remaining registers are read-only and are loaded with newvalues from the chain descriptor whenever the channel reads a chain descriptor from memory.Table 9-3.DMA Controller Unit RegistersSection, Register Name, Acronym (page)Section 9.14.1, “Channel Control Register - CCR” on page 9-26Section 9.14.2, “Channel Status Register - CSR” on page 9-27Section 9.14.3, “Next Descriptor Address Register - NDAR” on page 9-29Section 9.14.4, “Descriptor Address Register - DAR” on page 9-30Section 9.14.5, “Byte Count Register - BCR” on page 9-31Section 9.14.6, “PCI Address Register - PADR” on page 9-32Section 9.14.7, “PCI Upper Address Register - PUADR” on page 9-33Section 9.14.8, “Intel ® 80200 Processor Local Address Register - LADR” onpage 9-34Section 9.14.9, “Descriptor Control Register - DCR” on page 9-35Developer’s Manual 9-25