Intel 80312 I/O Companion Chip - ECEE

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Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge UnitTable 4-21. SSR Error Reporting Summary (Sheet 2 of 2)Error Bit in Primary StatusRegister (SSR)Error ConditionQualifying Bit in PrimaryCommand Register(BCR)Target Abort (target) - bit 11Upstream Delayed Read WhichReceived a Target Abort on thePrimary Bus. Set DuringCompletion Cycle on SecondaryBus.Upstream Delayed Write WhichReceived a Target Abort on thePrimary Bus. Set DuringCompletion Cycle on SecondaryBus.Upstream Posted Write WhichReceived a Target Abort on thePrimary Bus and the TransactionWas Still Active on the SecondaryBusN/AN/AN/A4-78 Developer’s Manual
Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.12 Initialization and Reset RequirementsWhen the Primary bus P_RST# is removed from the Primary interface, the PCI-to-PCI bridge unitis in an inactive mode. The bridge responds only to Type 0 configuration cycles with the PrimaryIDSEL input active. System configuration software is responsible for setting up the bridge unit forcorrect operation. Refer to the PCI Local Bus Specification, Revision 2.2 and the PCI-to-PCIBridge Architecture Specification, Revision1.1.4.12.1 Bridge ResetThe PCI-to-PCI bridge unit has two independent reset states; one for the Primary interface and onefor the Secondary interface. The Secondary S_RST# signal is the logical OR of the Primaryinterface P_RST# and the Secondary Bus Reset bit in the BCR. The assertion of the Secondaryinterface S_RST# output is asynchronous with respect to the Secondary output clocks(S_CLKOUT[5:0]); to support this, there exists a combinatorial path from the Primary P_RST#input and the Secondary Bus Reset bit in the BCR to the Secondary PCI bus S_RST# output. Thedeassertion of the S_RST# output is synchronous with the Secondary output clocks. The bridgedoes not take any action when Secondary bus S_RST# is driven active by another device.When the Secondary Bus Reset Bit in the BCR is set and subsequently cleared by software, theIntel ® 80312 I/O companion chip can also be programmed to send an interrupt to the Intel ® 80200processor. This is done using the Secondary Decode Enable Register - SDER.During the reset sequence (no more than three clocks from the assertion of P_RST# on the Primaryinterface) the Secondary PCI Bus Arbitration Unit must park the Secondary bus on the Secondarybus interface. Refer to Section 7.2.1.3, “Priority Example with Six Bus Masters” on page 7-5 fordetails on bridge parking.4.12.2 Configuring the PCI-to-PCI BridgeFor the bridge unit to operate in a system environment, several things must be properly initialized.The procedure below is required for all PCI-to-PCI bridges and is included here for completeness.1. The Primary Bus Number, Secondary Bus Number and Subordinate Bus Number must beprogrammed with valid bus numbers. This must be done to allow the configuration software toprobe the configuration space of downstream buses.2. When I/O accesses must be forwarded downstream, the IOBR and IOLR register pair must beprogrammed to proper values and then the I/O Space Enable bit set in the PCR register. TheISA Enable bit of the BCR register should be set when the system includes ISA or EISA buses.3. When Memory accesses must be forwarded downstream, both the Memory Mapped I/O rangeand Prefetchable Memory range must be defined by programming MBR/MLR andPMBR/PMLR register pairs. When only one address range is required the PMBR/PMLRregister pair can be programmed with the same values as the MBR/MLR register pair. After allfour memory registers are valid, the Memory Enable bit in the PCR register can be set.4. When VGA Compatible address forwarding is required, the VGA Enable bit (bit 3 of theBCR) must be set. Also, the Memory Space Enable and the I/O Space Enable bits must be setin order for VGA Compatible addressing to be operational. This mode forwards VGACompatible Memory and I/O accesses downstream independent of the MBR/MLR,PMBR/PMLR, and IOBR/IOLR register pairs. This mode should be enabled when a VGAcompatible device exists on the Secondary PCI bus.Developer’s Manual 4-79
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Intel ® 80200 Processor based on I
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Intel 80312 I/O Companion Chip - ECEE

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