Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.3 Messaging UnitThe Messaging Unit (MU) transfers data between the PCI system and the Intel ® 80312 I/Ocompanion chip and notifies the respective system when new data arrives. The MU is described inChapter 6, “Messaging Unit”.The primary PCI window for messaging transactions is always the first 4 Kbytes of the inboundtranslation window defined by the Primary Inbound ATU Base Address Register (PIABAR) andthe Primary Inbound ATU Limit Register (PIALR).Access to the Messaging Unit from the secondary PCI interface is supported through acombination of the PCI-to-PCI Bridge Unit and the Secondary ATU. If bit 12 of the ATUCR is set,the first 4 KB of the SATU address is not claimed by the SATU but is allowed to be claimed by thesecondary interface of the bridge. This address space must be within the range that is normallydecoded and forwarded from secondary to primary by the bridge. Once the transaction is forwardedthrough the bridge, the setting of bit 12 allows the Intel ® 80312 I/O companion chip to act as amaster (bridge) and slave (ATU/Messaging Unit) at the same time on the primary interface. Referto Section 5.7.37, “ATU Configuration Register - ATUCR” on page 5-98 for details of bit 12. Thebridge unit does not perform any special “steering” of transactions from the secondary interface tothe primary ATU/MU. The upstream bridge transaction must have a valid MU address to access theMU (first 4 KB of primary ATU address space).All of the Messaging Unit errors are reported in the same manner as PATU errors. Error conditionsand status can be found in the PATUSR and the PATUISR, see Section 5.6, “ATU ErrorConditions” on page 5-39.5-30 Developer’s Manual