Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.2.1.3 Inbound Read TransactionAn inbound read transaction is initiated by a PCI master (on either the primary or secondary PCIbus) and is targeted at either Intel ® 80312 I/O companion chip local memory or a Intel ® 80312 I/Ocompanion chip memory-mapped register. The read transaction is propagated through the inboundtransaction queues (ITQ1 and ITQ2) and read data is returned through the inbound read queue(IRQ).All inbound read transactions are processed as delayed read transactions. The ATUs PCI interfaceclaims the read transaction and forwards the read request through to the internal bus and returns theread data to the PCI bus. Data flow for an inbound read transaction on the PCI bus is summarizedin the following statements:• The ATU claims the PCI read transaction when the PCI address is within the inboundtranslation window defined by ATU Inbound Base Register and Inbound Limit Register.• When one of the ITQs is empty, the PCI address and command are latched into the availableITQ and a Retry is signalled to the initiator.• If an ITQ is currently holding transaction information from a previous delayed read, thecurrent transaction information is compared to the previous transaction information (based onthe setting of the DRC Alias bit in Section 5.7.37, “ATU Configuration Register - ATUCR” onpage 5-98).IfthereisamatchandthedataisintheIRQ,returnthedatatothemasteronthePCI bus. If there is a match or the data is not available, a Retry is signaled with no other actiontaken. If there is not a match and there is an ITQ available, latch the transaction information,signal a Retry and initiate a delayed transaction. If there is not a match and there is not an ITQavailable, signal a Retry with no other action taken.— For the case where there is a match on the transaction information and the IRQ iscurrently being filled, memory read streaming is possible.— If an address parity error is detected, address parity response defined in Section 5.6 is used.• Once read data is driven onto the PCI bus from the IRQ, it continues until one of the followingis true:— The initiator completes PCI transaction. Unread data left in the IRQ is flushed.— An internal bus Target Abort was detected. In this case, the Q-word associated with theTarget Abort is never entered into the IRQ, and therefore is never returned.— The IRQ becomes empty. In this case, the PCI interface signals a Disconnect with data tothe initiator on the last data word available.The slave ATU interface delivers 64-bit read data when REQ64# was asserted and 32-bitread data when REQ64# was deasserted.• If the master inserts waitstates on the PCI bus, the ATU PCI slave interface waits with nopremature disconnects.• If a data parity error occurs signified by PERR# asserted from the master, no action is takenby the slave interface. Refer to Section 5.6.2.3.• If the transaction on the internal bus resulted in a master abort, the completion cycle is allowedto master abort on the PCI interface. The ITQ for this transaction is flushed (Section 5.6.1.).• When the first Q-word read on the internal bus is target-aborted, either a target-abort or adisconnect with data is signaled to the initiator. This is based on the ATU ECC Target AbortEnable bit (bit 0 of the PATUIMR for PATU and bit 0 of the SATUIMR for the SATU). If set, atarget abort is used, when clear, a disconnect is used.Developer’s Manual 5-11