Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipMemory Controller3.4.1 Single-Bit Error DetectionWhen enabled, the MCU interrupts the Intel ® 80200 processor when the ECC logic detects asingle-bit error by setting the appropriate bit in the MCISR register. The Intel ® 80200 processorknows the interrupt was caused by a single-bit error by polling the ELOG0 or ELOG1 register. TheMCU ensures that correct data is transferred onto the internal bus but the interrupt handler isresponsible for scrubbing the error in the array (refer to Section 3.2.4.4, “Scrubbing” onpage 3-31).An example flow for a single-bit error with error detection and reporting enabled is:• A single-bit ECC error is detected on the data bus (DQ[63:0]) bytheMCU.• The MCU fixes the error prior to sending the data onto the internal bus.• The MCU clears ELOG0[8] indicating a single-bit error.• The MCU records the master of the transaction that resulted in an error in ELOG0[18:16]• The MCU loads ELOG0[7:0] with the syndrome that indicated the error.• The MCU loads ECAR0[31:2] with address where the error occurred.• Since the Intel ® 80200 processor needs to scrub the error in the array, the MCU sets MCISR[0]to 1 (assuming it is not already set).— Setting any bit in the MCISR causes an IRQ# interrupt to the Intel ® 80200 processor.• Software polls the interrupt status register. Bit 0 set to 1 indicates that the first error hasoccurred.• Software polls ELOG0 and ECAR0 and scrubs the error at the location specified by ECAR0.• Software writes a 1 to MCISR[0] thereby clearing it.When software does not perform error scrubbing, the probability of an unrecoverable double-biterror increases for the memory location containing the single-bit error.ECARx and ELOGx remain registered until software explicitly clears them.When a second error occurs before software clears the first by resetting MCISR[0] or MCISR[1],the error is recorded in the remaining ELOGx/ECARx register. When none are available, the erroris not logged but the MCU carries out the action described in Table 3-15.3-42 Developer’s Manual