Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.6.6 PCI Write TransactionsThe Intel ® 80312 I/O companion chip supports memory write and I/O write transactions from bothsides of the bridge unit. Memory write transactions are claimed when they are within theMBR/MLR or PMBR/PMLR address pairs on the Primary bus and outside the register pairs on theSecondary bus. I/O Write transactions are claimed when they are within the IOBR/IOLR writetransactions on the Primary bus and outside the address pair on the Secondary bus. Refer to the PCILocal Bus Specification, Revision 2.2 for full details on memory and I/O write transactions.Memory write commands will be attempted as 64-bit transactions (see Section 4.6.3). I/O andconfiguration write commands are always performed as 32-bit operations.The bridge supports both posted and delayed write memory transactions. I/O and configurationwrite transactions are always delayed transactions. The Posting Disable bit must be clear in theExtended Bridge Control Register (EBCR) to allow posting to occur from either interface of thebridge. When this bit is set, all write transactions are processed as delayed transactions.4.6.6.1 Delayed Write TransactionsA Delayed write transaction is very similar to a Delayed read transaction. The bridge will claim thetransaction on the initiating bus by asserting DEVSEL# and latch the address, command, byteenables into a Transaction Queue, and data into a Delayed Write Completion (DWC) Queue. It willthen signal a Retry to the initiator.Delayed write transactions are limited to one data cycle of 4 bytes for I/O writes, configurationwrites, and for memory writes performed with posting disabled.Delayed write transactions are used for:• I/O Writes• Configuration Writes• All memory writes when the Posting Disable bit in the Extended Bridge Control Register(EBCR) is set. This means the bridge limits all write commands to one PCI data phase(4 bytes) when this bit is set.The bridge then initiates the same command on the target bus. Once the target bus has beenobtained, the bridge propagates write data from the initiating bus to the target bus. The bridge willkeep the request information in a Transaction Queue and a DWC queue. The request information isthe address, command (including REQ64#), byte enables, parity (when enabled), and data.Once the write data has been successfully transferred to the target by assertion of IRDY# andTRDY# on the target bus, the bridge can now accept the repeated write command from the originalinitiator. At this time, the bridge will accept the request and attempt to match it with the transactioninformation in a Transaction Queue. The bridge must match the address, command, REQ64#, byteenables, parity (when parity is enabled), and data in order to signal a termination other than Retryto the initiator. The bridge unit will use the following terminations for delayed write cycles:• Completion termination when the transaction on the target bus terminated normally.• Master-Abort termination when the transaction on the target bus terminated with Master-Abortor normal termination (see Section 4.10.1.4).• Target-Abort termination when the transaction on the target bus terminated with Target-Abort.The initiator must repeat the write transaction exactly with the same address, REQ64#, byteenables, command, parity, and data or the bridge will treat the transaction as a new request. Whenthe initiator does not repeat the write transaction, the data and associated information may bediscarded (see Section 4.11.4).4-42 Developer’s Manual