Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipMemory Controller3.2.1.1 Internal Bus InterfaceThe Internal Bus Interface block supports internal bus protocol which is a subset of PCI protocol.3.2.1.2 Address DecodeThe Address Decode block is responsible for decoding the internal bus address and determiningwhen the MCU should claim the internal bus transaction. There are three address ranges that theMCU responds to.Flash Memory SpaceSDRAM Memory SpaceThe Flash memory space is defined with Flash Base Address Registers(FEBR0, FEBR1) and Flash Bank Size Registers (FBSR0, FBSR1). Thetransaction is intended for a Flash bank address falling between the baseregister (FEBRx) and the base plus the Flash size register (FBSRx).The SDRAM memory space is defined the SDRAM Base AddressRegister (SDBR) and SDRAM Boundary Registers (SBR0, SBR1). Thetransaction is intended for SDRAM bank addressings between the baseregister (SDBR) and the boundaries programmed with SBR0 and SBR1.The Address Decode block also records and maintains the open SDRAMpages. The MCU can keep a maximum of eight pages opensimultaneously. This block keeps track of these pages and determineswhen the internal bus transaction hits an open page. For more detailsabout the page hit/miss determination, see Section 3.2.3.3, “PageHit/Miss Determination” on page 3-16.Memory-Mapped Register SpaceThe MCU MMR memory space is 1500H to 15FFH. The registers aredetailed in Section 3.6, “Register Definitions” on page 3-44.3.2.1.3 Configuration RegistersThe Configuration Registers block contains all of the memory-mapped registers listed inSection 3.6, “Register Definitions” on page 3-44. These registers define the memory subsystemconnected to the Intel ® 80312 I/O companion chip. The status registers indicate the current MCUstatus.3.2.1.4 SDRAM State MachineThe SDRAM State Machine controls the protocol for SDRAM transactions.3.2.1.5 Flash State MachineThe Flash State Machine controls the protocol for Flash transactions.3.2.1.6 Refresh CounterThe Refresh Counter block keeps track of when the SDRAM devices need to be refreshed. Therefresh interval is programmed in the RFR. Once the 10-bit refresh counter reaches theprogrammed interval, the SDRAM state machine issues a refresh command to the SDRAMdevices. When a transaction is currently in progress, the SDRAM State Machine waits for thecompletion of the transaction to issue the refresh cycle. See Section 3.2.3.9, “SDRAM RefreshCycle” on page 3-26 for more details.3-4 Developer’s Manual