Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge UnitThe PCI interface is responsible for completing the posted write transaction to a PCI agent usingthe address/data in the PMW Queue. The data flow for the posted write transaction on the targetPCI bus is summarized in the following statements:• The master interface on the target PCI bus will request the PCI bus when posted writetransaction address is at the head of the PMW Queue and transaction ordering has beensatisfied (see Section 4.7.2). Once the bus is granted, the target PCI interface will write the PCIaddress from the PMW Queue to the PCI bus and wait for the transaction to be claimed.• When an address parity error is detected by the assertion of SERR# on the target interface, theerror is recorded. The action taken by the interface depends on the targets response to theparity error. When a master abort is used, see the following section.• When a master-abort is signaled, the master-abort condition is used. This could be eitherflushing the write data, asserting P_SERR#, or signaling a disconnect. Refer toSection 4.10.1.4 for details.• Once the PCI write transaction is claimed, the PCI interface will transfer data from the PMWQueue to the PCI bus. When ACK64# is asserted, data is transferred 64-bits at a time. WhenACK64# is deasserted, data is transferred 32-bits at a time. Data is transferred to the bus untilone of the following is true:— The PCI target signals Disconnect.— The PCI target signals a Target-Abort. In this case, the PMW Queue is flushed and thetransaction is aborted.— The PMW Queue become empty signifying that the transaction is finished. This results ina master completion.• When the transfer is an MWI, the bridge target bus interface may have to insert masterwaitstates to guarantee to transfer of an entire cacheline of data (defined by the value in theCLS register).• When a data parity error is detected by the target (PERR# driven) and it is not a result of anerror propagated from the initiating interface, the bridge master interface logs the error andasserts P_SERR#, when enabled, on the Primary bus. Refer to Section 4.11.2.3 for details.4-60 Developer’s Manual