Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge Unit4.15.9 Header Type Register - HTRHeader Type Register bits adhere to the definitions in the PCI Local Bus Specification,Revision 2.2. This register indicates the layout of bytes 10H to 3FH of the bridge configurationspace. The most significant bit indicates whether or not the device is multi-function and is definedas a 1 for multi-function device in the PCI-to-PCI Bridge Architecture Specification, Revision1.1.(Refer to Section 5.2.4, “PCI Multi-Function Device Swapping/Disabling” on page 5-24 forexceptions to this statement.)Table 4-32.Header Type Register- HTRIOPAttributes7 4 0rw rw rw rw rw rw rw rwPCIAttributesrorororororororoPCI Configuration Offset0EHIntel ® 80200 Processor Local Bus Address0000 100EHAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description7 1 2Single Function/Multi-Function Device - This bit identifies whether or not the Intel ® 80312 I/O companionchipisasingleormulti-functionPCIdevice.TheIntel ® 80312 I/O companion chip is considered amulti-function device.06:00 000001 2PCI Header Type - This bit field tells the system initialization code what type of PCI header isimplemented. The Intel ® 80312 I/O companion chip has a PCI-to-PCI bridge header as defined inPCI-to-PCI Bridge Architecture Specification, Revision 1.1.4-94 Developer’s Manual