Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPerformance Monitoring Unit11.3.4 Mode 3: Secondary PCI Bus and External AgentsProgramming Mode3 (M3) in the ESR enables performance monitoring on the secondary PCI bus.In addition, performance monitoring is done for external agents (Intel ® 80312 I/O companion chip,Master0, Master1, Master2) on the secondary PCI bus. Master0 indicates the external PCI devicethat is connected to the REQ0 and GNT0 signals of the internal arbiter in the Intel ® 80312 I/Ocompanion chip. The nomenclature is similar for all other external PCI masters; Master 1 throughMaster 5. There are four external agents monitored including the Intel ® 80312 I/O companion chip.All counters are clocked at the secondary PCI bus frequency. The following sections describe themonitored events in Mode 3.11.3.4.1 M3_SPCIbus_idleThis duration event increments the counter every PCI idle cycle. An idle cycle occurs when there isno activity on the bus due to data being transferred and/or the bus is not in an overhead cycle. Anoverhead cycle is a cycle when a master owns the bus, however the master is unable to send data orthe target is unable to receive data - hence no data is transferred.11.3.4.2 M3_SPCIbus_busyDuration event increments counter every PCI data cycle. Data cycles comprise two instances:• Intel ® 80312 I/O companion chip as master on bus is involves data transfers to other masters.• External masters initiate data transfers to either the Intel ® 80312 I/O companion chip or toother masters on the bus.11.3.4.3 M3_SPCI_IOP_acqThis duration event counts number of clocks spent by the Intel ® 80312 I/O companion chip(includes the bridge, dma Ch-2, and satu) acquiring the secondary PCI interface. The counterincrements on every clock cycle after the Intel ® 80312 I/O companion chip has requested use ofthe secondary PCI bus but has not actively driven the secondary PCI bus as a master. The counteralso increments for all clock cycles when this agent’s Request Signal is asserted but bus ownershipcurrently belongs to another master. This is an event primitive, used in conjunction with anotherevent primitive (number of grants granted to Intel ® 80312 I/O companion chip) to calculate theaverage acquisition latency for the processor.11.3.4.4 M3_SPCI_IOP_ownThis duration event counts the duration for which the Intel ® 80312 I/O companion chip is themaster on the secondary PCI interface. The counter increments on every clock cycle during whichthe Intel ® 80312 I/O companion chip is the bus master.11.3.4.5 M3_D0_acqThis duration event counts the number of clocks spent by PCI Master 0 acquiring the PCI interface.The counter increments on every clock cycle after the device has requested use of the PCI bus buthas not actively driven the PCI bus as a master. The counter also increments for all clock cycleswhen this agent’s Request Signal is asserted but bus ownership currently belongs to another master.This is an event primitive, used in conjunction with another event primitive (number of grantsgranted to PCI Master 0) to calculate the average acquisition latency for the device.Developer’s Manual 11-11