Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.7.36 ATU Power Management Control/Status Register - APMCSRPower Management Control/Status bits adhere to the definitions in the PCI Bus PowerManagement Interface Specification, Revision 1.1. This 16-bit register is the primary control andstatus interface for the power management extended capability.Table 5-64.ATU Power Management Control/Status Register - APMCSRIOPAttributes15 12 8 4 0ro rv rv rv rv rv rv ro rv rv rv rv rv rv rw rwPCIAttributesrorvrvrvrvrvrvrorvrvrvrvrvrvrw rwIntel ® 80200 Processor Local Bus Address0000 1284HPCI Configuration Offset84- 85HAttribute Legend:RV = ReservedPR = PreservedRS = Read/SetRW = Read/WriteRC = Read ClearRO = Read OnlyNA = Not AccessibleBit Default Description15 0 2PME_Status - This function is not capable of asserting the PME# signal in any state, since PME# is notsupported by the Intel ® 80312 I/O companion chip, thus the value of PME_Status is set to 0 2 and isread-only.14:9 00H ReservedPME_En - This bit is hardwired to read-only 08 0 2 since this function does not support PME# generation2 from any power state.7:2 000000 2 Reserved1:0 00 2PowerState-This2-bitfieldisusedbothtodeterminethecurrentpowerstateofafunctionandtosetthe function into a new power state. The definition of the values is:00 2 -D001 2 - D1 (Unsupported)10 2 - D2 (Unsupported)11 2 -D3 hotThe Intel ® 80312 I/O companion chip supports only the D0 and D3 hot states.Developer’s Manual 5-97