Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI-to-PCI Bridge UnitTable 4-12.Downstream Memory Read Prefetch SizeNon-Prefetchable Memory AddressPrefetchable Memory Address SpaceSpaceRead CommandCLS 1 = 8 (32 bytes) CLS = 16 (64 bytes) CLS = 8 (32 bytes) CLS = 16 (64 bytes)MemoryRead Upto32Bytes Upto64Bytes Upto4Bytes Upto4BytesMemory Read Line Up to 32 Bytes 2 Upto64Bytes Upto4Bytes Upto4BytesMemory ReadMultipleUpto64Bytes Upto64Bytes Upto4Bytes Upto4Bytes1. CLS - Cache Line Size Defined by the Cache Line Size Register within the bridge configuration space2. Up to 64 Bytes when the Downstream MRL Prefetch Size Bit is set in the Queue Control Register (See Section 4.15.35)Table 4-13.Upstream Memory Read Prefetch SizeNon-Prefetchable Memory AddressPrefetchable Memory Address SpaceSpaceRead CommandCLS 1 =8(32bytes) CLS = 16 (64 bytes) CLS = 8 (32 bytes) CLS = 16 (64 bytes)MemoryRead Upto32Bytes Upto64Bytes Upto4Bytes Upto4BytesMemory Read Line Up to 32 Bytes 2 Up to 64 Bytes 3 Upto4Bytes Upto4BytesMemory ReadMultipleUpto256Bytes Upto256Bytes Upto4Bytes Upto4Bytes1. CLS - Cache Line Size Defined by the Cache Line Size Register within the bridge configuration space2. Up to 64 Bytes when the Upstream MRL Prefetch Size Bit is set in the Queue Control Register (See Section 4.15.35)3. Up to 128 Bytes when the Upstream MRL Prefetch Size Bit is set in the Queue Control Register (See Section 4.15.35)When the value in the CLS is anything other than eight or 16, the read prefetch behavior will bethat of a CLS value of eight (32 bytes).When selected read queue is large enough, MRL control bits within the Queue Control Register arecapable of promoting the Memory Read Line Command prefetch size to 2x the amount in previoustables, when the command is in the prefetchable address space. Refer to Section 4.15.35 for details.The MRL prefetch bits increase the maximum prefetch size attempted during an MRL transaction.I/O Read commands, Configuration Read, and all non-prefetchable read commands are limited toone 32-bit PCI data phase. The bridge reads and stores up to four bytes for these transaction types.The bridge signals a Disconnect to the initiator when the master requests more than one DWORD.The Delayed Completion transaction is the repeated memory read, I/O read, or configuration readtransaction from the original initiator. The bridge matches the address, command, REQ64#, andbyte enables of repeated transaction with those in the Transaction Queue and retrieves the datafrom the DRC queues. The bridge provides the requested data to the initiator and signals thetermination (other than Retry) that matches what was used on the target bus.The bridge will terminate the Delayed Completion transaction with:• Completion termination when the transaction on the target bus terminated normally.• Master-Abort termination or 1s ( number of 1s passed back, either 32-bit or 64-bit, is based on PCIbus size of initiating master, and in 64-bit bus size case, REQ64#/ACK64#) when the transactionon the target bus terminated with Master-Abort. See Section 4.10.1 for more information.• Target-Abort termination when the transaction on the target bus terminated with Target-Abort.• Disconnect termination when the transaction on the target bus terminated with Disconnectbefore the prefetch data amount was reached.Developer’s Manual 4-39