Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipPCI Address Translation Unit5.7.15 Determining Block Sizes for Base Address RegistersThe required address size and type can be determined by writing ones to a base address register andreading from the registers. By scanning the returned value from the least-significant bit of the baseaddress registers upwards, the programmer can determine the required address space size. Thebinary-weighted value of the first non-zero bit found indicates the required amount of space.Section 5-42 describes the relationship between the values read back and the byte sizes the baseaddress register requires.Table 5-42.Memory Block Size Read Response TableResponse After Writing all 1sto the Base Address RegisterSize(in Bytes)Response After Writing all 1sto the Base Address RegisterSize(in Bytes)FFFFFFF0H 16 FFF00000H 1 MFFFFFFE0H 32 FFE00000H 2 MFFFFFFC0H 64 FFC00000H 4 MFFFFFF80H 128 FF800000H 8 MFFFFFF00H 256 FF000000H 16 MFFFFFE00H 512 FE000000H 32 MFFFFFC00H 1K FC000000H 64 MFFFFF800H 2K F8000000H 128 MFFFFF000H 4K F0000000H 256 MFFFFE000H 8K E0000000H 512 MFFFFC000H 16K C0000000H 1 GFFFF8000H 32K 80000000H 2 GFFFF0000H64KRegister not implemented,noFFFE0000H128K00000000HFFFC0000H256Kaddress spacerequired.FFF80000H512KAs an example, assume that FFFF.FFFFH is written to the ATU Primary Inbound Base AddressRegister (PIABAR) and the value read back is FFF0.0004H. Bit zero is a zero, so the devicerequires memory address space. Bits 2:1 are 00 2 , so the memory can be located anywhere within32-bit address space (4 Gbytes). Bit three is one, so the memory does supports prefetching.Scanning upwards starting at bit four, bit twenty is the first one bit found. The binary-weightedvalue of this bit is 1,048,576, indicated that the device requires 1 Mbyte of memory space.Both the Primary and Secondary Inbound ATU Base Address Registers and the Expansion ROMBase Address Register use their associated limit registers to enable which bits within the baseaddress register are read/write and which bits are read only (0). This allows the programming ofthese registers in a manner similar to other PCI devices even though the limit is variable.Table 5-43.ATU Base Registers and Associated Limit RegistersBase Address Register Limit Register DescriptionPrimary Inbound ATUBase Address RegisterSecondary Inbound ATUBase Address RegisterExpansion ROM BaseAddress RegisterPrimary Inbound ATULimit RegisterSecondary Inbound ATULimit RegisterExpansion ROM LimitRegisterDefines the inbound translation window from theprimary PCI bus.Defines the inbound translation window from thesecondary PCI bus.Defines the window of addresses used by a primarybus master for reading from an Expansion ROM.5-76 Developer’s Manual