Intel 80312 I/O Companion Chip - ECEE

Intel ® 80312 I/O Companion ChipApplication Accelerator Unit10.5 Application Accelerator PriorityThe internal bus arbitration logic determines which internal bus master has access to the Intel ®80312 I/O companion chip internal bus. The Application Accelerator has an independent BusRequest/Grant signal pair to the internal bus arbitration logic. Chapter 7, Intel ® 80312 I/OCompanionChipArbitrationdescribes in detail the priority scheme between all of the bus masterson the internal bus.10.6 Programming Model State DiagramThe AAU programming model diagram is shown in Figure 10-12. Error condition states are notshown.Figure 10-12. Application Accelerator Programming Model State DiagramResetIDLESTATEREAD NADSTATERead NAD fromcurrent descriptorat ADARandloadANDARChain Resume = 0ABORT == 0 &&AAU Enable == 1 &&Chain Resume == 1 &&ANDAR == 0ANDAR == 0 ||Internal Bus errorTransfer Complete &&ANDAR == 0 &&Chain Resume == 1 &&!IB errorIB error ||ANDAR == 0 &&AAU Active = 0Chain Resume == 0 &&Transfer CompleteXOR TRANSFERSTATEABORT == 0 &&AAU Enable == 1 &&Chain Resume == 0 &&ANDAR != 0Internal Bus error!Internal Bus errorTransfer Complete &&ANDAR != 0READ DESCRIPTORSTATERead descriptorat ANDARChain Resume = 0AAU Active = 1ANDAR != 0 && !Internal Bus error10-18 Developer’s Manual