RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 16 LCD CONTROLLER/DRIVER 16.6 Common and Segment Signals Each pixel of the LCD panel turns on when the potential difference between the corresponding common and segment signals becomes higher than a specific voltage (LCD drive voltage, VLCD). The pixels turn off when the potential difference becomes lower than VLCD. Applying DC voltage to the common and segment signals of an LCD panel causes deterioration. To avoid this problem, this LCD panel is driven by AC voltage. (1) Common signals Each common signal is selected sequentially according to a specified number of time slices at the timing listed in Table 16-3. In the static display mode, the same signal is output to COM0 to COM3. In the three-time-slice mode, leave the COM3 pin open. COM Signal Number of Time Slices Static display mode Three-time-slice mode Four-time-slice mode Table 16-3. COM Signals COM0 COM1 COM2 COM3 R01UH0317EJ0004 Rev. 0.04 981 Feb. 22, 2013 Open
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 16 LCD CONTROLLER/DRIVER (2) Segment signals (a) R5F10CGx/R5F10DGx The segment signals correspond to 27 bytes of the LCD display data memory (F0300H to F0307H, F0309H, F030EH, F030FH, F0318H to F031BH, F031DH to F0323H, F0328H to F032CH) during an LCD display period, bits 0, 1, 2, and 3 of each byte are read in synchronization with COM0, COM1, COM2, and COM3, respectively. If a bit is 1, it is converted to the select voltage, and if it is 0, it is converted to the deselect voltage. The conversion results are output to the segment pins (SEG0 to SEG7, SEG9, SEG14 to SEG15, SEG24 to SEG27, SEG29 to SEG35, SEG40 to SEG44). (b) R5F10CLx/R5F10DLx The segment signals correspond to 39 bytes of the LCD display data memory (F0300H to F0309H, F030EH to F0313H, F0315H, F0317H to F032CH) during an LCD display period, bits 0, 1, 2, and 3 of each byte are read in synchronization with COM0, COM1, COM2, and COM3, respectively. If a bit is 1, it is converted to the select voltage, and if it is 0, it is converted to the deselect voltage. The conversion results are output to the segment pins (SEG0 to SEG9, SEG14 to SEG19, SEG21, SEG23 to SEG44). (c) R5F10CMx/R5F10DMx The segment signals correspond to 48 bytes of the LCD display data memory (F0300H to F032FH) during an LCD display period, bits 0, 1, 2, and 3 of each byte are read in synchronization with COM0, COM1, COM2, and COM3, respectively. If a bit is 1, it is converted to the select voltage, and if it is 0, it is converted to the deselect voltage. The conversion results are output to the segment pins (SEG0 to SEG47). (d) R5F10TPx/R5F10DPx The segment signals correspond to 53 bytes of the LCD display data memory (F0300H to F0334H) during an LCD display period, bits 0, 1, 2, and 3 of each byte are read in synchronization with COM0, COM1, COM2, and COM3, respectively. If a bit is 1, it is converted to the select voltage, and if it is 0, it is converted to the deselect voltage. The conversion results are output to the segment pins (SEG0 to SEG52). Check, with the information given above, what combination of front-surface electrodes (corresponding to the segment signals) and rear-surface electrodes (corresponding to the common signals) forms display patterns in the LCD display data memory, and write the bit data that corresponds to the desired display pattern on a one-toone basis. LCD display data memory bits 1 to 3 are not used for LCD display in the static display, and bit 3 is not used for three-time slot mode, respectively. So these bits can be used for purposes other than display. The higher 4 bits of “F0300H to F0334H” are fixed to 0. R01UH0317EJ0004 Rev. 0.04 982 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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RL78/D1A User’s Manual: Hardware
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